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| Home > Integration Test Registers > Processor integration testing > DBGITMISCIN Register (Miscellaneous Inputs) | |||
The DBGITMISCIN Register at offset 0xEFC is
read-only. Figure 13.3 shows
the register bit assignments.
Table 13.6 lists the register bit assignments for the DBGITMISCIN Register.
Table 13.6. DBGITMISCIN Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:12] | - | Reserved. Read Undefined. |
| [11] | DBGRESTARTm | Read value of the DBGRESTARTm input pin. |
| [10] | - | Reserved. Read Undefined. |
| [9:8] | ETMEXTOUTm | Read value of the ETMEXTOUTm[1:0] input pins. |
| [7:6] | - | Reserved. Read Undefined. |
| [5] | nETMWFIREADYm | Reads the nETMWFIREADYm input pin. Although this pin is active LOW, the value of this bit matches the physical state of the signal: 0 = input pin is LOW (asserted) 1 = input pin is HIGH (deasserted). |
| [4:3] | - | Reserved. Read Undefined. |
| [2] | nFIQm | Read value of nFIQm input pin. |
| [1] | nIRQm | Read value of nIRQm input pin. |
| [0] | EDBGRQm | Read value of EDBGRQm input pin. |