B.3.2. Cycle counts if destination is the PC

Table B.4 shows the cycle timing behavior for data processing instructions if their destination is the PC. You can substitute ADD with any data processing instruction except for a CLZ. A CLZ with the PC as the destination is an Unpredictable instruction.

For condition code failing cycle counts, the cycles for the non-PC destination variants must be used.

Table B.4. Data Processing instruction cycle timing behavior if destination is the PC

Example instructionCycles

Early Reg

Late Reg

Result latency

ADD pc, <Rn>, #<immed>9---Normal cases to PC
ADD pc, <Rn>, <Rm>9---
ADD pc, <Rn>, <Rm>, LSL #<immed>9<Rm>--Requires a shifted source register
ADD pc, <Rn>, <Rm>, LSL <Rs>9

<Rm>, <Rs>

--Requires a register controlled shifted source register

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