B.13.2.  Load Multiples, where the PC is in the register list

The processor includes a 4-entry return stack that can predict procedure returns. Any LDM to the PC that does not restore the SPSR to the CPSR, is predicted as a procedure return.

In all cases the base register, <Rn>, is a Very Early Reg.

Table B.18 shows the cycle timing behavior of Load Multiples, where the PC is in the register list.

Table B.18. Cycle timing behavior of Load Multiples, with PC in the register list (64-bit aligned)

Example instructionCyclesMemory cyclesResult latencyComments
LDMIA <Rn>,{...,pc}
m[a]n[b]2,…Correct return stack prediction
LDMIA <Rn>,{...,pc}
m[a] + 8n[b]2,…Incorrect return stack prediction
LDMIA <cond> <Rn>,{...,pc}
m[a]n[b]2,…Correct condition prediction and correct return stack prediction
LDMIA <cond> <Rn>,{...,pc}
m[a] + 7n[b]2,…Incorrect condition prediction
LDMIA <cond> <Rn>,{...,pc}
m[a] + 8n[b]2,…Correct condition prediction and incorrect return stack prediction

[a] Where m is the number of cycles for this instruction if the PC were treated as a normal register.

[b] Where n is the number of memory cycles for this instruction if the PC were treated as a normal register.


Note

The Cycle timing behavior that Table B.18 shows also covers PUSH and POP instructions that behave like store and load multiple instructions with base register writeback.

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