B.3.1. Cycle counts if destination is not PC

Table B.3 shows the cycle timing behavior for data processing instructions if their destination is not the PC. You can substitute ADD with any of the data processing instructions identified in the opening paragraph of this section.

Table B.3. Data Processing Instruction cycle timing behavior if destination is not PC

Example instructionCycles

Early Reg

Late Reg

Result latency

ADD <Rd>, <Rn>, #<immed>1--1Normal cases.
ADD <Rd>, <Rn>, <Rm>1--1
ADD <Rd>, <Rn>, <Rm>, LSL #<immed>1<Rm>-1Requires a shifted source register.
ADD <Rd>, <Rn>, <Rm>, LSL <Rs>1

<Rm>, <Rs>


Requires a register controlled shifted source register.

MOV <Rd>, <Rm>1-<Rm>1Simple MOV case. Must not set the flags or require a shifted source register.

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