B.23.2. Permitted combinations

Table B.28 lists the permitted instruction combinations. Any instruction can be conditional or flag-setting unless otherwise stated. Only the exact instruction combinations listed in Table B.28 can be dual issued, provided you ensure the instruction combinations obey the rules specified in Dual issue rules.

Table B.28. Permitted instruction combinations

Dual issue caseFirst instructionSecond instruction
Case A

Any instruction other than load/store multiple/double, flag-setting multiply, non-VFP coprocessor operations, miscellaneous processor control instructions[a], or floating point instructions if floating point logic is not included in the processor

B #immed

IT

NOP

Case A-F[b]Any floating point instructions, excluding load/store multiple, double-precision CDP instructions, VCVT.F64.F32, and VMRS and VMSR.
Case B1

LDR <Rt>, [<Rn>, #<imm>][c]

LDR <Rt>, [<Rn>, <Rm>][c]

LDR <Rt>, [<Rn>, <Rm>, LSL #1, 2 or 3][c]

Any data processing instruction that does not require a shift by a register value.[d]

Any bitfield, saturate or bit-packing instruction.[e]

Any signed or unsigned extend instruction.[f]

Any SIMD add or subtract instruction.[g]

Other miscellaneous instructions.[h]

Case B1-F[b]

Any single-precision CDP[i], excluding "VMOV.F32 <Sd>, #<imm>", VNEG.F32, VABS.F32, VCVT.F64.F32, VDIV.F32, and VSQRT.F32.

32-bit transfers to and from the floating-point register file[l].

Case B2

STR <Rt>, [<Rn>, #<imm>][c]

As for Case B1.
Case B2-F[b]As for Case B1-F
Case C

MOV <Rd>, #immed[j][k]

MOVW <Rd>, #immed[j]

MOV <Rd>, <Rm>[j]

Any data processing instruction.[d]

Any bitfield, saturate or bit-packing instruction.[e]

Any signed or unsigned extend instruction.[f]

Any SIMD add or subtract instruction.[g]

Other miscellaneous instructions.[h]

Case C-F[b]32-bit transfers to and from the floating-point register file[l].
Case F1[b],[m]Any single-precision CDP[i], excluding “VMOV.S32 <Sd>, #<imm>", VCVT.F64.F32, VABS.F32, and VNEG.F32.As for case C or C-F.
Case F2_ld[b]VLDR.F32[n]As for Case B1 or Case B1-F
Case F2_st[b]VSTR.F32[n]

As for Case B1.

Any single-precision CDP[i], excluding multiply-accumulate instructions[o].

32-bit transfers to and from the floating-point register file[l].

Case F2D[b]VLDR.F64[n]As for Case B1.
Case F3[b]

32-bit transfers to and from the floating-point register file[l]

"VMOV.F32, <Sd>, <Sm>", VABS.F32, and VNEG.F32.

As for Case F2_st.
Case F4[b]Any instruction that does not set flags, other than load/store multiple/double, non-VFP coprocessor operations, multi-cycle multiply instructions[p], double-precision floating point CDP instructions, VCVT.F64.F32, or a miscellaneous processor control instruction[a]

Any single-precision CDP[i], excluding "VMOV.F32 <Sd>, #<imm>", VNEG.F32, VABS.F32, VCVT.F64.F32, VDIV.F32, and VSQRT.F32.

32-bit transfers to and from the floating-point register file[l].

Case F6[b]VMRS r15, FPSCRAs for Case A.

[a] These are processor state updating instructions, synchronization instructions, SVC, BKPT, prefetch abort and Undefined Instructions.

[b] This case can only occur if the optional floating-point functionality has been configured for the Cortex-R5F processor, see Configurable options.

[c] You can substitute LDR with LDRB, LDRH, LDRSB, or LDRSH. You can also substitute STR with STRB or STRH.

[d] Data processing instructions are ADC, ADD, ADDW, AND, ASR, BIC, CLZ, CMN, CMP, EOR, LSL, LSR, MOV, MOVT, MOVW, MVN, ORN, ORR, ROR, RRX, RSB, SBC, SUB, SUBW, TEQ, and TST.

[e] Bitfield, saturate, and bit-packing instructions are BFC, BFI, PKHBT, PKHTB, QADD, QDADD, QDSUB, QSUB, SBFX, SSAT, SSAT16, UBFX, USAT, and USAT16.

[f] Signed or unsigned extend instructions are SXTAB, SXTAB16, SXTAH, SXTB, SXTB16, SXTH, UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.

[g] SIMD add and subtract instructions are QADD16, QADD8, QASX, SQUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSUB16, SSUB8, SSAX, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USUB16, USUB8, and USAX.

[h] Other miscellaneous instructions are RBIT, REV, REV16, REVSH, and SEL.

[i] Single-precision CDPs are VABS.F32, VNEG.F32, "VMOV.F32 <Sd>, #<imm>", VMLA.F32, VMLS.F32, VNMLS.F32, VNMLA.F32, VMUL.F32, VNMUL.F32, VADD.F32, VSUB.F32, VDIV.F32, VSQRT.F32, VCMP.F32, VCMPE.F32, VCVT.F64.F32, VCVT.F32.U32, VCVT.F32.S32, VCVT.F32.U16, VCVT.F32.S16, VCVTR.U32.F32, VCVT.U32.F32, VCVTR.S32.F32, VCVT.S32.F32, VCVT.U16.F32, and VCVT.S16.F32.

[j] Must not be flag-setting.

[k] Immediate value must not require a shift.

[l] 32-bit transfers to or from the floating point register file include single or half-double floating point register transfers, including "VMOV <Sn>, <Rt>", "VMOV.F32 <Dn[x]>, <Rt>", "VMOV.F32 <Rt>, <Dn[x]>", and "VMOV <Rt>, <Sn>", but excluding VMRS and VMSR.

[m] When the first instruction is a floating point multiply-accumulate, and the second instruction is a 32-bit transfer to the floating-point register file, case F1 can only occur if the two instructions have different destination registers.

[n] Any addressing modes.

[o] Single-precision floating-point multiply-accumulate instructions are VMLA.F32, VMLS.F32, VNMLS.F32, and VNMLA.F32.

[p] Multi-cycle multiply instructions are SMMUL, SMMLA, SMMLS, MUL, MLA, MLS, SMULL, SMLAL, UMAAL, UMULL, and UMLAL.


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