B.13.1. Load and Store Multiples, other than load multiples including the PC

In all cases the base register, <Rn>, is a Very Early Reg.

Table B.17 shows the cycle timing behavior of load and store multiples including the PC.

Table B.17. Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC

Example instructionCyclesCycles with base register write-backMemory cyclesResult latency (LDM)Result latency (base register)
First address 64-bit aligned  
 
LDMIA <Rn>,{R1}
11121
 
LDMIA <Rn>,{R1,R2}
1212,22
 
LDMIA <Rn>,{R1,R2,R3}
2222,2,32
 
LDMIA <Rn>,{R1,R2,R3,R4}
2322,2,3,33
 
LDMIA <Rn>,{R1,R2,R3,R4,R5}
3332,2,3,3,43
 
LDMIA <Rn>,{R1,R2,R3,R4,R5,R6}
3432,2,3,3,4,44
 
LDMIA <Rn>,{R1,R2,R3,R4,R5,R6,R7}
4442,2,3,3,4,4,54
First address not 64-bit aligned 
 
LDMIA <Rn>,{R1}
12122
 
LDMIA <Rn>,{R1,R2}
2222,32
 
LDMIA <Rn>,{R1,R2,R3}
2322,3,33
 
LDMIA <Rn>,{R1,R2,R3,R4}
3332,3,3,43
 
LDMIA <Rn>,{R1,R2,R3,R4,R5}
3432,3,3,4,44
 
LDMIA <Rn>,{R1,R2,R3,R4,R5,R6}
4442,3,3,4,4,54
 
LDMIA <Rn>,{R1,R2,R3,R4,R5,R6,R7}
4542,3,3,4,4,5,55

Note

The Cycle timing behavior that Table B.17 shows also covers PUSH and POP instructions that behave like store and load multiple instructions with base register write-back.

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