8.5. About the caches

The L1 memory system can be configured to include instruction and data caches of varying sizes. You can configure whether each cache controller is included and, if it is, configure the size of each cache independently. The cached instructions or data are fetched from external memory using the AXI-master L2 memory interface. The cache controllers use RAMs that are integrated into the Cortex-R5 processor during implementation.

Any access that is not for a TCM or peripheral port is handled by the appropriate cache controller. If the access is to non-shared Cacheable memory, and the cache is enabled, a lookup is performed in the cache and, if found in the cache, that is, a cache hit, the data is fetched from or written into the cache. When the cache is not enabled and for Non-cacheable or shared memory, the accesses are performed using the AXI-master interface.

Both caches allocate a memory location to a cache line on a cache miss because of a read, that is, all Cacheable locations are Read-Allocate (RA). In addition, the data cache can allocate on a write access if the memory location is marked as Write-Allocate (WA). When a cache line is allocated, the appropriate memory is fetched into a linefill buffer by the AXI-master interface before being written to the cache. See Linefill buffers and the AXI master interface. The linefill buffers always fetch the requested data first, return it, and then fetch the rest of the cache line. This enables the data read to be used by the pipeline without waiting for the linefill to complete and is known as critical word first and non-blocking behavior. If subsequent instructions require data from the same cache line, this can also be returned when it has been fetched without waiting for the linefill to complete, that is, the caches also support streaming. If an error is reported to the AXI-master interface for a linefill, the linefill does not update the cache RAMs, but an abort is only generated if the error was reported on the critical word.

If all the cache lines in a set are valid, to allocate a different address to the cache, the cache controller must evict a line from the cache.

Writes accesses that hit in the cache are written into the cache RAMs. If the memory location is marked as Write-Through (WT), the write is also performed on the AXI-master interface, so that the data stored in the RAM remains coherent with the external memory system. If the memory is Write-Back (WB), the cache line is marked as dirty, and the write is only performed on the AXI-master interface when the line is evicted. When a dirty cache line is evicted, the data is passed to the Eviction Buffer in the AXI-master interface to be written to the external memory system. See Eviction buffer for more information.

The cache controllers also manage the cache maintenance operations described in Cache maintenance operations.

Each cache can also be configured with either parity or ECC error checking schemes. If an error checking scheme is implemented and enabled, then the tags associated with each line, and data read from the cache are checked whenever a lookup is performed in the cache. See Cache error detection and correction for more information.

For more information on the general rules about memory attributes and behavior, see the ARM Architecture Reference Manual.

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