B.3.3. Example interlocks
Most data processing instructions are single-cycle and can
be executed back-to-back without interlock cycles, even if there
are data dependencies between them. The exceptions to this are when
shifts are used.
The registers that the shifter requires are Early Regs and
require an additional cycle of result availability before use. For
example, the following sequence introduces a 1-cycle interlock,
and takes three cycles to execute:
ADD R1,R2,R3
ADD R4,R5,R1 LSL #1
The second source register, that is not shifted, does not
incur an extra data dependency check. Therefore, the following sequence
takes two cycles to execute:
ADD R1,R2,R3
ADD R4,R1,R9 LSL #1
Register controlled shifts
The register containing the shift distance is an Early Reg.
For example, the following sequence takes three cycles to execute:
ADD R1, R2, R3
ADD R4, R2, R4, LSL R1
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