B.12. Load and Store Double instructions

This section describes the cycle timing behavior for the LDRD and STRD instructions.

The LDRD and STRD instructions:

Table B.15 shows the cycle timing behavior for LDRD and STRD instructions.

Table B.15. Load and Store Double instructions cycle timing behavior

Example instructionCycles

Cycles with base writeback

Memory cycles

Result latency (LDRD)

Result latency (base register)

Address is doubleword aligned      
 LDRD R0, R1, <addr_md_1cycle>[a]1212, 22
 LDRD R0, R1, <addr_md_3cycle>a3414, 44
Address not doubleword aligned      
 LDRD R0, R1, <addr_md_1cycle>a2222, 32
 LDRD R0, R1, <addr_md_3cycle>a4424, 54

[a] See Table B.16 for an explanation of <addr_md_1cycle> and <addr_md_3cycle>.

Table B.16 shows the explanation of <addr_md_1cycle> and <addr_md_3cycle> used in Table B.15.

Table B.16. <addr_md_1cycle> and <addr_md_3cycle> LDRD example instruction explanation

Example instructionVery Early RegComments
 LDRD <Rt>, <Rt2>, [<Rn>, #<imm>] (!)<Rn>If post-increment addressing, pre-increment addressing with an immediate offset or a positive register offset, then 1-issue cycle
 LDRD <Rt>, <Rt2>, [<Rn>, <Rm>] (!)<Rn>, <Rm>
 LDRD <Rt>, <Rt2>, [<Rn>], #<imm><Rn>
 LDRD <Rt>, <Rt2>, [<Rn>], +/-<Rm><Rn>, <Rm>
 LDRD <Rt>, <Rt2>, [<Rn>, -<Rm>] (!)<Rn>,<Rm>If pre-increment addressing with a negative register offset, then 3-issue cycles

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