B.4. QADD, QDADD, QSUB, and QDSUB instructions

This section describes the cycle timing behavior for the QADD, QDADD, QSUB, and QDSUB instructions.

These instructions perform saturating arithmetic. They have a result latency of two. The QDADD and QDSUB instructions must double and saturate the register <Rn> before the addition. This register is an Early Reg.

Table B.5 shows the cycle timing behavior for QADD, QDADD, QSUB, and QDSUB instructions.

Table B.5. QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior

InstructionsCyclesEarly RegResult latency
QADD, QSUB1-2
QDADD, QDSUB1<Rn>2

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