A.6. TCM interface signals

Table A.17 shows the ATCM port signals.

Table A.17. ATCM port signals

SignalDirectionDescription
ATCDATAINm[63:0]InputData from ATCM
ATCPARITYINm[13:0]InputECC code from ATCM
ATCERRORmInputError detected by ATCM[a]
ATCWAITmInputWait from ATCM
ATCLATEERRORmInputLate error from ATCM[a]
ATCRETRYmInputAccess to ATCM must be retried[a]
ATCADDRPTYmOutputParity formed from ATCM address output[b]
ATCEN0mOutputEnable for ATCM lower word, bit range [31:0]
ATCEN1mOutputEnable for ATCM upper word, bit range [64:32]
ATCWEmOutputWrite enable for ATCM
ATCADDRm[22:3]OutputAddress for ATCM data RAM
ATCBYTEWRm[7:0]OutputByte strobes for direct write
ATCSEQmOutputATCM RAM access is sequential
ATCDATAOUTm[63:0]OutputWrite data for ATCM data RAM
ATCPARITYOUTm[13:0]OutputWrite ECC code for ATCM
ATCACCTYPEm[2:0]Output

Determines access type:

b001 = Load/Store

b010 = Fetch

b100 = DMA

b100 = MBIST[c].

[a] This signal is ignored when bit [0] of the Auxiliary Control Register is set to 0, see c1, Auxiliary Control Register.

[b] Only generated if the processor is configured to include TCM address bus parity.

[c] The MBIST interface has no way of signaling a wait. If it is accessing the TCM, and the TCM signals a wait, the AXI slave pipeline stalls and the data arrives later. However, no signal is sent to the MBIST controller to indicate this.


Table A.18 shows the B0TCM port signals.

Table A.18. B0TCM port signals

SignalDirectionDescription
B0TCDATAINm[63:0]InputData from B0TCM
B0TCPARITYINm[13:0]InputECC code from B0TCM
B0TCERRORmInputError detected by B0TCM[a]
B0TCWAITmInputWait from B0TCM
B0TCLATEERRORmInputLate error from B0TCM[a]
B0TCRETRYmInputAccess to B1TCM must be retried[a]
B0TCADDRPTYmOutputParity formed from B0TCM address output[b]
B0TCWEmOutputWrite enable for B0TCM
B0TCEN0mOutputEnable for B0TCM lower word, bit range [31:0]
B0TCEN1mOutputEnable for B0TCM upper word, bit range [64:32]
B0TCADDRm[22:3]OutputAddress for B0TCM data RAM
B0TCBYTEWRm[7:0]OutputByte strobes for direct write
B0TCSEQmOutputB0TCM RAM access is sequential
B0TCDATAOUTm[63:0]OutputWrite data for B0TCM data RAM
B0TCPARITYOUTm[13:0]OutputWrite ECC code for B0TCM
B0TCACCTYPEm[2:0]Output

Determines access type:

b001 = Load/Store

b010 = Fetch

b100 = DMA

b100 = MBIST[c].

[a] This signal is ignored when bit [1] of the Auxiliary Control Register is set to 0, see c1, Auxiliary Control Register.

[b] Only generated if the processor is configured to include TCM address bus parity.

[c] The MBIST interface has no way of signaling a wait. If it is accessing the TCM, and the TCM signals a wait, the AXI slave pipeline stalls and the data arrives later. However, no signal is sent to the MBIST controller to indicate this.


Table A.19 shows the B1TCM port signals.

Table A.19. B1TCM port signals

SignalDirectionDescription
B1TCDATAINm[63:0]InputData from B1TCM
B1TCPARITYINm[13:0]InputECC code from B1TCM
B1TCERRORmInputError detected by B1TCM[a]
B1TCRETRYmInputAccess to B1TCM must be retried[a]
B1TCLATEERRORmInputLate error from B1TCM[a]
B1TCWAITmInputWait from B1TCM
B1TCADDRPTYmOutputParity formed from B1TCM address output[b]
B1TCWEmOutputWrite enable for B1TCM
B1TCEN0mOutputEnable for B1TCM lower word, bit range [31:0]
B1TCEN1mOutputEnable for B1TCM upper word, bit range [64:32]
B1TCADDRm[22:3]OutputAddress for B1TCM data RAM
B1TCBYTEWRm[7:0]OutputByte strobes for direct write
B1TCSEQmOutputB1TCM RAM access is sequential
B1TCDATAOUTm[63:0]OutputWrite data for B1TCM data RAM
B1TCPARITYOUTm[13:0]OutputWrite ECC code for B1TCM
B1TCACCTYPEm[2:0]Output

Determines access type:

b001 = Load/Store

b010 = Fetch

b100 = DMA

b100 = MBIST[c].

[a] This signal is ignored when bit [2] of the Auxiliary Control Register is set to 0, see c1, Auxiliary Control Register.

[b] Only generated if the processor is configured to include TCM address bus parity.

[c] The MBIST interface has no way of signaling a wait. If it is accessing the TCM, and the TCM signals a wait, the AXI slave pipeline stalls and the data arrives later. However, no signal is sent to the MBIST controller to indicate this.


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