9.3.7. AXI transaction splitting

The processor splits AXI bursts when it accesses addresses across a cache line boundary, that is, a 32-byte boundary. An instruction that accesses memory across one or two 32-byte boundaries generates two or three AXI bursts respectively. The following examples show this behavior. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

For example, LDMIA R10, {R0-R5} loads six words from memory. The number of AXI transactions generated by this instruction depends on the base address, R10:

Table 9.20 shows possible values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for an LDR or LDM1 to Non-cacheable Normal memory that crosses a cache line boundary.

Table 9.20. Non-cacheable LDR or LDM1 crossing a cache line boundary

Address[4:0]ARADDRMmARBURSTMmARSIZEMmARLENMm
0x1D (byte 29)0x1CIncr32-bit1 data transfer
0x00Incr32-bit1 data transfer
0x1E (byte 30)0x1EIncr16-bit1 data transfer
0x00Incr64-bit1 data transfer
0x1F (byte 31)0x1FIncr8-bit1 data transfer
0x00Incr32-bit1 data transfer

Table 9.21 shows possible values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for an STRH to Non-cacheable Normal memory that crosses a cache line boundary.

Table 9.21. Cacheable write-through or Non-cacheable STRH crossing a cache line boundary

Address[4:0]AWADDRMmAWBURSTMmAWSIZEMmAWLENMmWSTRBMm
0x1F (byte 31)0x1FIncr8-bit1 data transferb10000000
0x00Incr16-bit1 data transferb00000001

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