B.10. Processor state updating instructions

This section describes the cycle timing behavior for the MSR, MRS, CPS, and SETEND instructions. Table B.11 shows processor state updating instructions and their cycle timing behavior.

Table B.11. Processor state updating instructions cycle timing behavior

MRS1All MRS instructions
MSR SPSR1All MSR instructions to the SPSR
MSR5All other MSR instructions to the CPSR
CPS<effect> <iflags>1Interrupt masks only
CPS<effect> <iflags>, #<mode>1Mode changing

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