B.14. RFE and SRS instructions

This section describes the cycle timing for the RFE and SRS instructions.

These instructions:

In all cases the base register is a Very Early Reg.

Table B.19 shows the cycle timing behavior for RFE and SRS instructions.

Table B.19. RFE and SRS instructions cycle timing behavior

Example instructionCyclesMemory cycles
Address doubleword aligned
 
RFEIA <Rn>
101
 
SRSIA #<mode>
11
Address not doubleword aligned
 
RFEIA <Rn>
112
 
SRSIA #<mode>
22

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