B.15. Synchronization instructions

This section describes the cycle timing behavior for the CLREX, DMB, DSB, ISB, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, and SWPB instructions

In all cases the base register, Rn, is a Very Early Reg. Table B.20 shows the synchronization instructions cycle timing behavior.

Table B.20. Synchronization instructions cycle timing behavior

InstructionCyclesMemory cyclesResult latency
LDREX <Rt>, <Rn>112
LDREXB <Rt>, <Rn>112
LDREXH <Rt>, <Rn>112
LDREXD <Rt>, <Rn>[a]112
STREX <Rd>, <Rt>, <Rn>112
STREXB <Rd>, <Rt>, <Rn>112
STREXH <Rd>, <Rt>, <Rn>112
STREXD <Rd>, <Rt>, <Rt2>, <Rn>[a]112
SWP <Rt>, <Rt2>, <Rn>223
SWPB <Rt>, <Rt2>, <Rn>223

[a] Address must be 64-bit aligned.

The synchronization instructions DMB, DSB, and ISB stall the pipeline for a variable number of cycles, depending on the current state of the memory system.

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