B.13.3.  Example Interlocks

The following sequence that has an LDM instruction takes six cycles to execute, because R7 has a result latency of five cycles:

LDMIA R0, {R1-R7}
ADD R10, R10, R7

The following sequence that has an STM instruction takes five cycles to execute:

STMIA R0, {R1-R7}
ADD 	R7, R10, R11

The following sequence has a result latency hidden by issue cycles. It takes five cycles to execute.

LDMIA R0, {R1-R7}
ADD R10, R10, R3

The following sequence that has a POP instruction takes seven cycles to execute, because R9 has a result latency of six cycles:

POP {R1-R9}
ADD R10, R10, R9

The following sequence that has a PUSH instruction takes five cycles to execute:

PUSH {R1-R7}
ADD R10,R10,R7

Note

In the examples, R0 and sp are 64-bit aligned addresses. The instructions PUSH and POP always use the sp register for the base address.

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