10.2. Power management

Each CPU in the Cortex-R5 processor supports four different power modes from Run to Shutdown, with decreasing levels of power consumption, but increasing entry and exit costs. The modes are summarized in the following table.

Table 10.1. Power management modes

ModeCPU clock gatedCPU logic poweredCPU RAMs poweredExit to Run mode requires
Run NoYesYes-
StandbyWhen idleYesYesPipeline restart
DormantYesNoYes

Pipeline restart

Restore registers and configuration from memory

ShutdownYesNoNo

Pipeline restart

Restore registers and configuration from memory

Invalidate caches and reinitialize caches and TCMs


If the processor is implemented with twin CPUs, then each CPU can be in a mode independent of the other, provided CPU1 is never in a higher power mode than CPU0 when CPU0 is in Dormant or Shutdown mode. Regardless of the state of the CPUs, the logic for the ACP interfaces and the debug-APB interfaces remain powered up.

A CPU can only enter Dormant or Shutdown modes if it is implemented with the appropriate power gating circuitry and clamp logic, and is integrated into a system with a power controller.

This section describes:

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