9.2.1. Identifiers for AXI bus accesses

Accesses on the AXI bus use ID values as follows:

Outstanding write/read access on different IDs

This means, for example, that a Non-cacheable (NC) read and linefills can be outstanding on the AXI bus simultaneously as long as the IDs are different.

At the same time, there can be:

  • up to seven outstanding reads, each with one of seven different ID values, that consists of:

    • a data side read NC access, RID0

    • an instruction side read NC access or an instruction side read Cacheable access, RID1

    • five outstanding data side linefills on the AXI bus, RID3 - RID7.

  • up to two IDs on outstanding writes, that consist of:

    • single or burst NC writes or write-through (WT) writes, WID0

    • evictions, WID1.

Outstanding write accesses with the same ID

When the address and data of the first write are both put on AXI bus, another write request with same ID can be sent when the address or data channel is released. For example, the new address can be sent with the same ID, before the target accepts the data of the first write.

Note

  • The AXI master does not generate two outstanding read accesses with the same ID.

  • The AXI master does not interleave write data from two different bursts, even if the bursts have different IDs.

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