9.1. About the L2 interface

This section describes the processor L2 interface. The L2 interface consists of:

The processor is designed for use in larger chip designs using the Advanced Microcontroller Bus Architecture (AMBA) AXI and AHB protocols. Instruction fetches and data accesses that the L1 memory system does not service, and peripheral accesses, are performed through the AXI-master interface or one of the peripheral interfaces. See:

External AXI masters, that can include the processor itself, can use the AXI slave interface to access the processor RAMs. You can use the AXI slave interface for DMA access into and out of the TCMs or to perform software test of the cache RAMs. See AXI slave interface.

The ACP interface enables the Cortex-R5 processor to observe memory transactions that other AXI masters perform, and keep the L1 caches coherent with those transactions. See Accelerator Coherency Port interface for more information about the ACP interface.

You can configure all of the ports associated with the L2 interfaces with bus-ECC. The bus-ECC feature uses additional signals to communicate redundant information, enabling the detection or correction of errors that occur on the bus signals. See Bus ECC for more information.

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