B.16. Coprocessor instructions

This section describes the cycle timing behavior for the MCR and MRC instructions to CP14, the debug coprocessor or CP15, the system control coprocessor.

The precise timing of coprocessor instructions is tightly linked with the behavior of the relevant coprocessor. Table B.21 shows the coprocessor instructions cycle timing behavior. Table B.21 shows the best case numbers.

Table B.21. Coprocessor instructions cycle timing behavior

InstructionCyclesResult latencyComments
MCR6--
MCR<cond>6-Condition code passes
4-Condition code fails
MRC66-
MRC<cond>66Condition code passes
44Condition code fails

Note

Some instructions such as cache operations take more cycles.

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