1.5.1. CPU configurations

A Cortex-R5 processor group can consist of either one or two CPUs. The number of CPUs included and the behavior of these CPUs within the group depends on the configuration used. This section describes the CPU arrangements supported and the functionality of each arrangement.

Single CPU

This configuration includes a single CPU.

Twin CPU

This configuration includes two individual and decoupled CPUs, and a single, optional ACP. It offers higher performance than a standard single CPU configuration. Each CPU has its own cache RAMs, debug logic and bus interfaces to the rest of the SoC. There is only one ACP port in the group. Accesses on this port are kept coherent with both CPUs in the group. For more information about ACP coherency, see Accelerator Coherency Port interface. The CPUs do not interact within the processor group boundary but might interact elsewhere in the SoC. Contact your system integrator for more information about programming a device that includes a twin-CPU configuration.

You can configure some aspects of the two CPUs separately, for example cache size. See Table 1.1 for more information about which configuration options can be configured independently.

There is no internal hardware to maintain coherency between the two CPUs in a twin CPU Cortex-R5 group. Loss of coherency occurs if one CPU tries to access dirty data that is in the cache of the other CPU. For example, if CPU0 attempts to transfer a frame of data to CPU1, using a write-back cacheable memory region, then the frame valid bit might miss in the CPU0 cache and be updated in level-2 memory, while some or all of the frame data can hit in the CPU0 cache and not be updated in level-2 memory. This represents a loss of coherency, because CPU1 can detect a valid frame but reads out-of-date frame data. For more information about coherency, see Coherency.

Redundant CPU

In this configuration, there is a single functional CPU and an optional ACP. The configuration also includes a second redundant copy of the majority of the CPU logic, and a redundant copy of the ACP logic if an ACP is configured. The redundant logic is driven by the same inputs as the functional logic. In particular, the redundant CPU logic shares the same cache RAMs as the functional CPU. Therefore only one set of cache RAMs is required. The redundant logic operates in lock-step with the CPU, but does not directly affect the processor behavior in any way. The processor outputs to the rest of the system, and the CPU outputs to the cache RAMs, are driven exclusively by the functional CPU.

Comparison logic can be included, during implementation, to compare the outputs of the redundant logic and the functional logic. These comparators can detect a single fault that occurs in either set of logic because of radiation or circuit failure. When used in conjunction with RAM error detection schemes, the system can be protected from faults.

The input signals DCCMINP[7:0] and DCCMINP2[7:0] and the output signals DCCMOUT[7:0] and DCCMOUT2[7:0] enable the comparators to communicate with the rest of the SoC.

ARM provides example comparison logic, but you can change this during implementation. If you are implementing a Redundant CPU configuration, contact ARM for more information.

Split/Lock

Two CPUs are included in this configuration. If an ACP is configured, a functional ACP and a redundant copy of the ACP logic is included. The processor group can operate in one of two modes:

Split mode

Operates as a twin-CPU configuration. Also known as performance mode.

Locked mode

Operates as a redundant CPU configuration. Also known as safety mode.

Switching between these modes is only permitted while the processor group is held in power-on reset. The input signals SLCLAMP and SLSPLIT are provided to enable the system to control the mode of the processor group. For more information about how to effect a change in processor mode, contact your system integrator.

If you are implementing a Split/Lock configuration, contact ARM for more information.

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