2.3.2. Reset modes

The reset signals in the processor enable you to reset different parts of the design independently. Table 2.1 shows the reset signals, and the combinations and possible applications that you can use them in.

Table 2.1. Reset modes

Reset modenRESETmDBG RESETmnPRESET DBGmnACP RESETnnSYSPO RESETnCPU HALTmApplication
Power-on reset0/xxxx0xPower-up reset, full-system reset. Hard or cold reset.
CPU reset011x1xWatchdog reset, soft reset or warm reset. Debug logic remains active to permit debugging through reset.
CPU power-up reset001x1xReset of CPU, on wake-up from dormant or shutdown modes.
Debug resetx00x1xDebugger and debug system reset.
ACP resetxxx01xCoherent peripheral reset.
Normal111111Normal run mode.
Halt111110Halt mode with CPU not fetching instructions, provided normal mode has not been entered since last reset

All reset signals are synchronized within the processor. You do not have to synchronize either edge of any of the reset signals. Unless otherwise stated, whenever nRESETm is asserted, it must be held asserted for at least four CLKIN cycles to ensure correct reset operation.

Note

If you are implementing either a dual-redundant core or a Split/Lock configuration, contact ARM for additional reset requirements.

This section of the manual describes:

Power-on reset

You must apply power-on or cold reset to the processor when power is first applied to the system. A power-on reset must consist of one of the following:

  • Assert nSYSPORESET and keep it asserted for at least four CLKIN cycles. See Figure 2.3.

    Figure 2.3. Power-on Reset

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  • Assert nSYSPORESET and nRESETm together, holding nRESETm asserted for at least four CLKIN cycles. See Figure 2.4.

    Figure 2.4. Power-on reset

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The processor implements synchronizers for nSYSPORESET. You do not have to synchronize either edge of nSYSPORESET.

After applying power-up reset to the processor, you must initialize various registers. See Initialization for more information.

CPU reset

A CPU or warm reset initializes the majority of the CPU logic, excluding the ACP and debug logic. Typically, you use CPU reset to reset a system that has been operating for some time, for example when a watchdog timer expires. The processor debug logic remains active, to permit debugging of the reset handling software.

You can safely reset either or both of the CPUs independently of the ACP.

It you are implementing a twin-CPU configuration you must ensure that a given CPU is quiescent before resetting it independently of the other CPU. A CPU is quiescent when all of the following are true:

  • either nWFEPIPESTOPPEDm or nWFIPIPESTOPPEDm is LOW

  • all transactions to the CPU from the system have completed

  • the system cannot issue new stimulus to the CPU.

CPU power-up reset

You must apply a CPU power-up reset when the processor wakes up from either dormant or shutdown mode. A CPU power-up reset must consist of the following:

  • Assert nRESETm and DBGRESETnm together and keep them asserted for at least four CLKIN cycles on wake-up from dormant or shutdown mode.

  • Assert nRESETm only and keep it asserted for at least four CLKIN cycles on wake-up from emulated dormant or emulated shutdown mode. The processor debug logic is kept active to permit debugging of the wake-up software.

After applying power-up reset to a CPU, you must initialize various registers. See Initialization for more information.

Debug Reset

A debug reset initializes all the debug and non-debug logic of the processor, excluding the ACP logic. This reset causes a debugger to lose connection to the processor, and therefore ARM recommends you should apply it only on request by the debugger, for example on detection of a fatal error condition.

ACP reset

An ACP reset resets the internal ACP logic and the ACP master and slave AXI ports. You can use ACP reset when the peripheral connected to the ACP port is reset. You must not assert ACP reset independently of the CPU resets, unless the ACP is quiescent. The ACP is quiescent when both of the following are true:

  • ACPIDLE is asserted

  • the system cannot issue new transactions to the ACP.

Normal operation

During normal operation, neither processor reset nor power-on reset is asserted. If the EmbeddedICE-RT logic is not used, the value of PRESETDBGmn does not matter.

Halt operation

When nCPUHALTm is asserted, and nSYSPORESET and nRESETm are deasserted, the CPU is out of reset, but the PFU is inhibited from fetching instructions. When the CPU is halted in this way, you can, for example, use the AXI slave interface to store instructions in the TCMs using DMA. You can then deassert nCPUHALTm and the PFU starts fetching the preloaded instructions from TCMs. When the CPU has started to fetch, nCPUHALTm must not be asserted again except when the CPU is reset.

Independent resets

When the Cortex-R5 processor is configured with an ACP, you can reset the CPU or CPUs independently of the ACP. In a twin-CPU configuration it is possible to reset the CPUs independently of each other. Each CPU and the ACP has its own AMBA ports, and in a typical system some or all of these are ultimately connected to the same bus infrastructure. In such a system, to preserve ongoing transactions from other masters, the bus infrastructure is not normally reset when only one of the CPUs or the ACP is reset. To avoid loss of synchronization between bus infrastructure that is not reset and logic that is reset, you must ensure that the logic is quiescent before reset is applied to it. If reset is applied to the bus infrastructure at the same time as the connected logic, the logic does not have to be quiescent.

A CPU is quiescent when:

  • nWFEPIPESTOPPEDm or nWFIPIPESTOPPEDm is asserted

  • all transactions to the CPU from the system have completed

  • the system can send no new stimulus to the CPU.

The ACP is quiescent when:

  • ACPIDLE is asserted

  • the system can send no new transactions to the ACP.

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