B.5. Media data-processing

Table B.6 shows media data-processing instructions and gives their cycle timing behavior.

All media data-processing instructions are single-cycle issue instructions. These instructions have result latencies of one or two cycles. Some of the instructions require an input register to be shifted, or manipulated in some other way before use and therefore are marked as requiring an Early Reg.

Table B.6. Media data-processing instructions cycle timing behavior

InstructionsCyclesEarly RegResult latency
SADD16, SSUB16, SADD8, SSUB81-1
UADD16, USUB16, UADD8, USUB81-1
SEL1-1
QADD16, QSUB16, QADD8, QSUB81-2
SHADD16, SHSUB16, SHADD8, SHSUB81-1
UQADD16, UQSUB16, UQADD8, UQSUB81-2
UHADD16, UHSUB16, UHADD8, UHSUB81-1
SSAT16, USAT161<Rn>1
SASX, SSAX1-1
UASX, USAX1-1
SXTAB, SXTAB16, SXTAH1<Rm>1
SXTB, SXTB16, SXTH1<Rm>[a]1
UXTB, UXTB16, UXTH1<Rm>[a]1
UXTAB, UXTAB16, UXTAH1<Rm>1
REV, REV16, REVSH, RBIT1<Rm>1
PKHBT, PKHTB1<Rm>1
SSAT, USAT1<Rm>1
QASX, QSAX1-2
SHASX, SHSAX1-1
UQASX, UQSAX1-2
UHASX, UHSAX1-1
BFC1<Rd>1
SBFX, UBFX1<Rn>1
BFI1<Rd>, <Rn>1

[a] A shift of zero makes <Rm> a Normal Reg for these instructions.


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