A.3. Configuration signals

Table A.2 shows the processor configuration signals. These signals must be tied off, or only changed under reset.

Table A.2. Configuration signals

SignalDirectionDescription
VINITHImInputReset V-bit value. When HIGH indicates HIVECS mode at reset. See c1, System Control Register for more information.
CFGEEInputReset EE-bit value. When HIGH indicates the implementation uses BE-8 mode for exceptions at reset. See c1, System Control Register for more information.
CFGIEInputInstruction side endianness, reflected in the IE-bit. When HIGH indicates that big endian instruction fetch is used. See c1, System Control Register for more information.
INITRAMAmInputReset value of ATCM enable bit. When HIGH indicates Tightly-Coupled Memory A, ATCM, enabled at reset. See c9, ATCM Region Register for more information.
INITRAMBmInputReset value of BTCM bit. When HIGH indicates Tightly-Coupled Memory B, BTCM, enabled at reset. See c9, BTCM Region Register for more information.
LOCZRAMAmInput

When HIGH indicates ATCM initial base address is zero and BTCM base address is implementation-defined.

When LOW indicates BTCM initial base address is zero and ATCM base address is implementation-defined.

TEINITInput

Reset TE-bit value. Determines exception handling state at reset. When set to:

0 = ARM

1 = Thumb.

See c1, System Control Register for more information.

CFGATCMSZm[3:0]Input

Selects the ATCM size. The encodings for the TCM sizes are:

b0000 = 0KB

b0011 = 4KB

b0100 = 8KB

b0101 = 16KB

b0110 = 32KB

b0111 = 64KB

b1000 = 128KB

b1001 = 256KB

b1010 = 512KB

b1011 = 1MB

b1100 = 2MB

b1101 = 4MB

b1110 = 8MB.

CFGBTCMSZm[3:0]Input

Selects the BTCM size. The encodings for the TCM sizes are:

b0000 = 0KB

b0011 = 4KB

b0100 = 8KB

b0101 = 16KB

b0110 = 32KB

b0111 = 64KB

b1000 = 128KB

b1001 = 256KB

b1010 = 512KB

b1011 = 1MB

b1100 = 2MB

b1101 = 4MB

b1110 = 8MB.

CFGNMFImInputWhen HIGH, enable nonmaskable Fast Interrupts. Reflected in the NMFI bit. See c1, System Control Register for more information.
ENTCM1IFmInput

Enable B1TCM interface. Use B0TCM only if this signal not tied HIGH.

PARECCENRAMm[2:0]Input

TCMs ECC check enable. Tie each bit HIGH to enable ECC checking on the appropriate TCM at reset. The bit allocations are as follows:

[2] = B1TCM[a]

[1] = B0TCMa

[0] = ATCM.

See c1, Auxiliary Control Register for more information.

PARITYLEVELInput

Selects between odd and even parity for caches and buses. See Chapter 8 Level One Memory System:

Tie LOW for even parity

Tie HIGH for odd parity.

ERRENRAMm[2:0]Input

TCMs external error enable. Tie each bit high to enable the external error signals for each TCM at reset. The bit allocations are as follows:

[2] = B1TCM

[1] = B0TCM

[0] = ATCM.

See c1, Auxiliary Control Register for more information.

RMWENRAMm[1:0][b]Input

RMW enable bits reset values. Tie each bit high to enable read-modify-write for TCM interfaces at reset.[c] The bit allocations are as follows:

[1] = BTCM

[0] = ATCM.

See c1, Auxiliary Control Register for more information.

SLBTCMSBmInput

Use most significant bit of BTCM address to select B1TCM if this signal is HIGH.

Use bit [3] of the BTCM address if this signal is LOW.

INITPPXmInputAXI peripheral interface is enabled out-of-reset.
INITPPHmInputAHB peripheral interface is enabled out-of-reset.
GROUPID[3:0]InputID of Cortex-R5 processor group (reflected in MPIDR).
PPHBASEm[31:12]InputBase address of AHB peripheral interface. Must be size-aligned.
PPHSIZEm[4:0]InputSize of AHB peripheral interface. See Table A.3 for the size encodings.
PPXBASEm[31:12]InputBase address of AXI peripheral interface. Must be size aligned.
PPXSIZEm[4:0]InputSize of AXI peripheral interface. See Table A.3 for the size encodings.
PPVBASEm[31:12]InputBase address of virtual-AXI peripheral interface. Must be within AXI PP and size-aligned. The virtual AXI peripheral interface region must be the same size or smaller than the AXI peripheral interface.
PPVSIZEm[4:0]InputSize of virtual-AXI peripheral interface. See Table A.3 for the size encodings.

[a] If the BTCM is configured with ECC, bit[2] and bit[1] must be the same value.

[b] Not used if 32-bit ECC is included.

[c] Not available in r0px revisions of the processor.


Table A.3 shows the peripheral interface size encodings.

Table A.3. Peripheral interface size encodings

EncodingSize
b000114KB
b001008KB
b0010116KB
b0011032KB
b0011164KB
b01000128KB
b01001256KB
b01010512KB
b010111MB
b011002MB
b011014MB
b011108MB
b0111116MB
b1000032MB
b1000164MB
b10010128MB
b10011256MB
b10100512MB
b101011GB
b101102GB
b101114GB

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