11.3. System registers

The VFPv3 architecture describes the following system registers:

Table 11.2 shows the VFP system registers in the Cortex-R5F FPU.

Table 11.2. VFP system registers

RegisterVMRS/VMSR <reg> fieldAccess typeReset state
Floating-Point System ID Register, FPSIDb0000Read-only0x4102315x[a]
Floating-Point Status and Control Register, FPSCRb0001Read/write0x00000000
Floating-Point Exception Register, FPEXCb1000Read/write0x00000000
VFP Feature Register 0, MVFR0b0111Read-only0x10110221
VFP Feature Register 1, MVFR1b0110Read-only0x00000011

[a] Bits [3:0] of the FPSID depend on the product revision. See the FPSID register description for more information.


Note

The FPSID, MVFR0, and MVFR1 Registers are read-only. Attempts to write these registers are ignored.

Table 11.3 shows that a Privileged mode is sometimes required to access a VFP system register. When a Privileged mode is required, an instruction that attempts to access a register in a nonprivileged mode takes the Undefined Instruction exception.

Table 11.3. Accessing VFP system registers

RegisterPrivileged accessUser access
FPEXC EN=0FPEXC EN=1FPEXC EN=0FPEXC EN=1
FPSIDPermittedPermittedNot permittedNot permitted
FPSCRNot permittedPermittedNot permittedPermitted
MVFR0, MVFR1PermittedPermittedNot permittedNot permitted
FPEXCPermittedPermittedNot permittedNot permitted

For a VFP system register to be accessible, it must follow the rules in Table 11.3 and the VFP must also be accessible according to the CPACR. See c1, Coprocessor Access Control Register for more information.

Note

All hardware ID information is privileged access only:

FPSID is privileged access only

This is a change in VFPv3 compared to VFPv2.

MVFR registers are privileged access only

User code must issue a system call to determine the features that are supported.

The following sections describe the VFP system registers:

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