B.1.4. Definition of terms

Table B.1 gives descriptions of cycle timing terms used in this appendix.

Table B.1. Definition of cycle timing terms

TermDescription
Memory CyclesThis is the number of cycles during which an instruction sends a memory access to the cache.
CyclesThis is the minimum number of cycles required to issue an instruction. Issue cycles that produce memory accesses to the cache are included, so Cycles is always greater than or equal to Memory Cycles.
Result Latency

This is the number of cycles before the result of this instruction is available to a Normal Reg of the following instruction. When the Result Latency of an instruction is greater than Cycles and the following instruction requires the result, the following instruction stalls for a number of cycles equal to Result Latency minus Cycles. If this value is negative, there are zero stall cycles.

Note

The Result Latency is counted from the first cycle of an instruction.

Normal Reg

The specified registers are required at the start of the Ex2 stage.

Late Reg

The specified registers are not required until the start of the Wr stage. Subtract one cycle from the Result Latency of the instruction producing this register.

Early Reg

The specified registers are required at the start of the Ex1 stage. Add one cycle to the Result Latency of the instruction producing this register.

Very Early Reg

The specified registers are required at the start of the Iss stage. Add two cycles to the Result Latency of the instruction producing this register, or one cycle if the instruction producing this register is an LDM, LDR, LDRD, LDREX, or LDRT. The lower Result Latency does not apply if this register is the base register of the load instruction producing this register, or if the load instruction is an LDRB, LDRBT, LDRH, LDRSB, or LDRSH.

InterlockThere is a data dependency between two instructions in the pipeline, resulting in the Iss stage being stalled until the processor resolves the dependency.

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