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Because the ARMv7-R architecture requires Jazelle® software compatibility, three Jazelle registers are implemented in the processor.
Table 3.7 shows the Jazelle register instruction summary and the response to the instructions.
Table 3.7. Jazelle register instruction summary
| Register | Instruction | Response |
|---|---|---|
| Jazelle ID |
| Read as zero Ignore writes |
| Jazelle main configuration |
| Read as zero Ignore writes |
| Jazelle OS control |
| Read as zero Ignore writes |
Because no hardware acceleration is present in the processor,
when the BXJ instruction is used, the BX instruction
is invoked.
| Copyright © 2010-2011 ARM. All rights reserved. | ARM DDI 0460C |
| Non-Confidential | ID021511 |
| PDF version | |
| Home > Programmers Model > Acceleration of execution environments |