A.4. Interrupt signals, including VIC interface signals

Table A.4 shows the interrupt signals including signals used on the VIC interface.

Table A.4. Interrupt signals

SignalDirectionDescription
nFIQmInputFast interrupt[a]. This signal can be asserted asynchronously if INTSYNCEN is HIGH.
nIRQmInputNormal interrupt[a]. This signal can be asserted asynchronously if INTSYNCEN is HIGH.
INTSYNCENInput

Tie HIGH if the interrupt inputs are asynchronous to CLKIN.

Tie LOW if the interrupt inputs are synchronous to CLKIN.

IRQADDRVmInputIndicates IRQADDRm is valid. This signal can be asserted asynchronously if IRQADDRVSYNCEN is HIGH.
IRQADDRVSYNCENInput

Tie HIGH if the IRQADDRVm input from the VIC is asynchronous to CLKIN.

Tie HIGH if the IRQADDRVm input from the VIC is synchronous to CLKIN.

IRQADDRm[31:2]Input

Address of the IRQ. This signal can be asserted asynchronously but must be stable when IRQADDRVm is asserted.

IRQACKmOutputAcknowledges interrupt.
nPMUIRQmOutputInterrupt request by Performance Monitor Unit (PMU).

[a] This signal is level-sensitive and must be held LOW until a suitable interrupt response is received from the processor.


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