11.5.2. IEEE 754 standard implementation choices

Some of the implementation choices permitted by the IEEE 754 standard and used in the VFPv3 architecture are described in the ARM Architecture Reference Manual.

NaN handling

All single-precision and double-precision values with the maximum exponent field value and a nonzero fraction field are valid NaNs. A most significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. Table 11.9 shows the default NaN values in both single-precision and double-precision.

Table 11.9. Default NaN values

 Single-precisionDouble-precision
Sign00
Exponent0xFF0x7FF
Fractionbit [22] = 1, bits [21:0] are all zerosbit [51] = 1, bits [50:0] are all zeros

Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows:

  • In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data transfer operations, NaNs are transferred without raising the Invalid Operation exception. For the non-arithmetic CDP instructions, VABS, VNEG, and VMOV, NaNs are copied, with a change of sign if specified in the instructions, without causing the Invalid Operation exception.

  • In default NaN mode, arithmetic CDP instructions involving NaN operands return the default NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions is the same as in full-compliance mode.

Table 11.10 summarizes the effects of NaN operands on instruction execution.

Table 11.10. QNaN and SNaN handling

Instruction typeDefault NaN modeWith QNaN operandWith SNaN operand
Arithmetic CDPOffThe QNaN or one of the QNaN operands, if there is more than one, is returned according to the rules given in the ARM Architecture Reference Manual.IOC[a] set. The SNaN is quieted and the result NaN is determined by the rules given in the ARM Architecture Reference Manual.
OnDefault NaN returns.IOCa set. Default NaN returns.
Non-arithmetic CDPOffNaN passes to destination with sign changed as appropriate.
On
VFCMP-Unordered compare.IOC set. Unordered compare.
VFCMPE-IOC set. Unordered compare.IOC set. Unordered compare.
Load/storeOffAll NaNs transferred.
On

[a] IOC is the Invalid Operation exception flag, FPSCR[0].


Comparisons

Comparison results modify the flags in the FPSCR Register. You can use the VMRS APSR_nzcv, FPSCR instruction (formerly FMSTAT) to transfer the current flags from the FPSCR Register to the CPSR Register. See the ARM Architecture Reference Manual for mapping of IEEE 754 standard predicates to ARM conditions. The flags used are chosen so that subsequent conditional execution of ARM instructions can test the predicates defined in the IEEE 754 standard.

Underflow

The Cortex-R5F FPU uses the before rounding form of tininess and the inexact result form of loss of accuracy as described in the IEEE 754 standard to generate Underflow exceptions.

In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE 754 standard, are flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual for information on flush-to-zero mode.

When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If the operation does not produce a tiny result, it returns the computed result, and the UFC flag, FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set if the result was also inexact.

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