8.5.4. Cache RAM organization

This section describes RAM organization in the following sections:

Tag RAM

The tag RAMs consist of four ways of up to 512 lines. The width of the RAM depends on the build options selected, and the size of the cache. The following tables show the tag RAM bits:

  • Table 8.4 shows the tag RAM bits when parity is implemented

  • Table 8.5 shows the tag RAM bits when ECC is implemented

  • Table 8.6 shows the tag RAM bits when neither parity nor ECC is implemented.

Table 8.4. Tag RAM bit descriptions, with parity

Bit in the tag cache lineDescription
Bit [23]Parity bit
Bit [22]Valid bit
Bits [21:0]Tag value

Table 8.5. Tag RAM bit descriptions, with ECC

Bit in the tag cache lineDescription
Bits [29:23]ECC code bits
Bit [22]Valid bit
Bits [21:0]Tag value

Table 8.6. Tag RAM bit descriptions, no parity or ECC

Bit in the tag cache lineDescription
Bit [22]Valid bit
Bits [21:0]Tag value

A cache line is marked as valid by bit [22] of the tag RAM. Each valid bit is associated with a whole cache line, so evictions always occur on the entire line.

Table 8.7 shows the tag RAM cache sizes and associated RAM organization, assuming no parity or ECC. For parity, the width of the tag RAMs must be increased by one bit. For ECC, the width of the tag RAMs must be increased by seven bits.

Table 8.7. Cache sizes and tag RAM organization

Cache sizeTag RAM organization
4KB4 banks 23 bits 32 lines
8KB4 banks 22 bits 64 lines
16KB4 banks 21 bits 128 lines
32KB4 banks 20 bits 256 lines
64KB4 banks 19 bits 512 lines

Dirty RAM

For the data cache only, the dirty RAM stores the following information:

  • two bits for line outer attributes for evictions

  • one line dirty bit

  • four ECC code bits if the ECC build option is selected.

The dirty RAM array consists of one bank of up to 512 12-bit lines, 4 ways x 3 bits. If ECC is enabled, the dirty RAM is 28 bits wide. Each line of dirty RAM contains all the information of the four ways for a given index.

Each time a dirty bit is written, the outer bits of the line and, if implemented, the ECC code bits, are also written. The dirty RAM is bit-enabled. Table 8.8 shows the organization of a dirty RAM line.

Table 8.8. Organization of a dirty RAM line

Bit in the dirty cache lineDescription
Bits [6:3]ECC bits, if implemented
Bits [2:1]

Outer attributes that are re-encoded on AWCACHEMm when an eviction is sent to the AXI bus:

01 = WB, WA

10 = WT

11 = WB, no WA

00 = Non-cacheable.

Bit [0]

Dirty bit


Data RAM

Data RAM is organized as eight banks of 32-bit wide lines, or in the instruction cache as four banks of 64-bit wide lines. This RAM organization means that it is possible to:

  • Perform a cache look-up with one RAM access, all banks selected together. This is done for nonsequential read operations. Figure 8.3 shows this.

  • Select the appropriate bank RAM for sequential read operations. Figure 8.4 shows this.

  • Write a line to the eviction buffer in one cycle, a 256-bit read access.

  • Fill a line in one cycle from the linefill buffer, a 256-bit write access.

Figure 8.3 shows a cache look-up being performed on all banks with one RAM access.

Figure 8.3. Nonsequential read operation performed with one RAM access.

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Figure 8.4 shows the appropriate bank RAM being selected for a sequential read operation.

Figure 8.4. Sequential read operation performed with one RAM access

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The data RAM organization is optimized for 64-bit read operations, because with the same address, two words on the same way can be selected.

Data RAM sizes depend on the build option selected, and are described in:

Data RAM sizes without parity or ECC implemented

Table 8.9 shows the organization for instruction and data caches when neither parity nor ECC is implemented.

Table 8.9. Instruction cache data RAM sizes, no parity or ECC

Cache sizeData RAMs
4KB, 4 1KB ways4 banks 64 bits 128 lines or 8 banks 32 bits 128 lines
8KB, 4 2KB ways4 banks 64 bits 256 lines or 8 banks 32 bits 256 lines
16KB, 4 4KB ways4 banks 64 bits 512 lines or 8 banks 32 bits 512 lines
32KB, 4 8KB ways4 banks 64 bits 1024 lines or 8 banks 32 bits 1024 lines
64KB, 4 16KB ways 4 banks 64 bits 2048 lines or 8 banks 32 bits 2048 lines

Table 8.10. Data cache data RAM sizes, no parity or ECC

Cache sizeData RAMs
4KB, 4 1KB ways8 banks 32 bits 128 lines
8KB, 4 2KB ways8 banks 32 bits 256 lines
16KB, 4 4KB ways8 banks 32 bits 512 lines
32KB, 4 8KB ways8 banks 32 bits 1024 lines
64KB, 4 16KB ways 8 banks 32 bits 2048 lines

Data RAM sizes with parity implemented

Table 8.11 shows the organization for instruction and data caches when parity is implemented. For parity error detection, one bit is added per byte, so four bits are added for each RAM bank.

Table 8.11. Instruction cache data RAM sizes, with parity

Cache size Data RAMs
4KB, 4 1KB ways 4 banks 72 bits 128 lines or 8 banks 36 bits 128 lines
8KB, 4 2KB ways 4 banks 72 bits 256 lines or 8 banks 36 bits 256 lines
16KB, 4 4KB ways 4 banks 72 bits 512 lines or 8 banks 36 bits 512 lines
32KB, 4 8KB ways 4 banks 72 bits 1024 lines or 8 banks 36 bits 1024 lines
64KB, 4 16KB ways 4 banks 72 bits 2048 lines or 8 banks 36 bits 2048 lines

Table 8.12. Data cache data RAM sizes, with parity

Cache size Data RAMs
4KB, 4 1KB ways 8 banks 36 bits 128 lines
8KB, 4 2KB ways 8 banks 36 bits 256 lines
16KB, 4 4KB ways 8 banks 36 bits 512 lines
32KB, 4 8KB ways 8 banks 36 bits 1024 lines
64KB, 4 16KB ways 8 banks 36 bits 2048 lines

Table 8.13 shows the organization of the data cache RAM bits when parity is implemented.

Table 8.13. Data cache RAM bits, with parity

RAM bits Description
Bit [35] Parity bit for byte[31:24]
Bit [34] Parity bit for byte[23:16]
Bit [33] Parity bit for byte[15:8]
Bit [32] Parity bit for byte[7:0]
Bits [31:0] Data[31:0]

Parity bits are grouped together in bits[35:32] so that data and parity bits are easily differentiated. With this design the parity bit is selected alongside the related data byte, so that when data is updated, the parity bit is also updated.

Data RAM sizes with ECC implemented

Table 8.14 shows the organization for the instruction cache when ECC is implemented. For ECC error detection, eight bits are added per 64 bits, so four bits are added for each RAM bank.

Table 8.14. Instruction cache data RAM sizes with ECC

Cache sizeData RAMs
4KB, 4 1KB ways 4 banks 72 bits 128 lines or 8 banks 36 bits 128 lines
8KB, 4 2KB ways 4 banks 72 bits 256 lines or 8 banks 36 bits 256 lines
16KB, 4 4KB ways 4 banks 72 bits 512 lines or 8 banks 36 bits 512 lines
32KB, 4 8KB ways 4 banks 72 bits 1024 lines or 8 banks 36 bits 1024 lines
64KB, 4 16KB ways 4 banks 72 bits 2048 lines or 8 banks 36 bits 2048 lines

Table 8.15 shows the organization for the data cache when ECC is implemented. For ECC error detection, seven bits are added per 32 bits, so seven bits are added for each RAM bank.

Table 8.15. Data cache data RAM sizes with ECC

Cache size Data RAMs
4KB, 4 1KB ways 8 banks 39 bits 128 lines
8KB, 4 2KB ways8 banks 39 bits 256 lines
16KB, 4 4KB ways 8 banks 39 bits 512 lines
32KB, 4 8KB ways 8 banks 39 bits 1024 lines
64KB, 4 16KB ways 8 banks 39 bits 2048 lines

Table 8.16 shows the organization of the data cache RAM bits when ECC is implemented.

Table 8.16. Data cache RAM bits, with ECC

RAM bits Description
Bits [39:32]ECC code bits for data [31:0]
Bits [31:0] Data [31:0]

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