9.4. AXI slave interface

The processor has a single AXI slave interface, with one port. The port is 64 bits wide and conforms to the AXI3 standard as described in the AMBA AXI Protocol Specification. Within the AXI standard, the slave port uses the extension signals AWCSELSm and ARCSELSm each as four separate chip select input signals to enable access to:

The external AXI system must generate the chip select signals. The slave interface routes the access to the required RAM.

If the processor is configured with bus-ECC, extension signals are also used for parity and ECC information. See Bus ECC for more information about bus-ECC.

The slave interface can run at the same frequency as the processor or at a lower, synchronous frequency. See AMBA interface clocking for more information. If asynchronous clocking is required, then an external asynchronous AXI register slice is required.

The AXI slave provides access to the TCMs and competes for access to the TCMs with the LSU and PFU. Both the LSU and PFU normally have a higher priority than the AXI slave.

If two BTCM ports are used, you can configure these to interleave in the address map, so any AXI slave access that is denied access to the BTCM on the first cycle of the access gains access on the second cycle when the LSU is using the other port, and can continue in lock-step with the LSU, assuming both are accessing sequential data. Accesses to the ATCM are more likely to encounter a conflict because there is only one port on the interface.

Memory BIST ports are routed through the AXI slave interface logic, to access the RAMs. Memory BIST access is assumed only to occur when no other accesses are taking place, and takes highest priority.

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