A.8. Debug interface signals

Table A.21 shows the debug interface signals. With the exception of PCLKENDBG, DBGRESETmn, and PRESETDBGmn, all these signals are only sampled or driven on CLKIN edges when PCLKENDBG is asserted.

Table A.21. Debug interface signals

SignalDirectionDescription
PCLKENDBGInputClock enable for APB buses.
PSELDBGmInputSelects the external debug interface.
PADDRDBGm[11:2]InputProgramming address.
PADDRDBG31mInputProgramming address.
PRDATADBGm[31:0]OutputRead data bus.
PWDATADBGm[31:0]InputWrite data bus.
PENABLEDBGmInputIndicates second, and subsequent, cycle of a transfer.
PREADYDBGmOutputExtends a APB transfer by the inserting wait states.
PSLVERRDBGmOutputSlave-generated error response.
PWRITEDBGmInput

Indicates access is a write transfer.

Distinguishes between a read, LOW, and a write, HIGH.

PRESETDBGmnInputReset debug domain debug logic.[a]
DBGRESETmnInputReset core domain debug logic.[a]

[a] Can be asserted asynchronously.


Table A.22 shows the debug miscellaneous signals.

Table A.22. Debug miscellaneous signals

SignalDirectionDescription
DBGENmInputDebug enable[a]
NIDENmInputNon-invasive debug enable[a]
EDBGRQmInputExternal debug request[a]
DBGACKmOutputDebug acknowledge
DBGRSTREQmOutputRequest for reset from debug logic
DBGTRIGGERmOutputExternal debug request taken
COMMRXmOutputDTRRX full
COMMTXmOutputDTRTX empty
DBGRESTARTmInputExternal restart request[a]
DBGRESTARTEDmOutputHandshake for DBGRESTARTm
DBGNOPWRDWNOutputNo power-down request
DBGROMADDR[31:12]InputDebug ROM physical address
DBGROMADDRVInputDebug ROM physical address valid
DBGSELFADDRm[31:12]InputDebug self-address offset
DBGSELFADDRVmInputDebug self-address offset valid

[a] Can be asserted asynchronously.


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