Cortex-R5 and Cortex-R5F Technical Reference Manual: A.8. Debug interface signals

A.8. Debug interface signals

Table A.21 shows the debug interface signals. With the exception of PCLKENDBG, DBGRESETmn, and PRESETDBGmn, all these signals are only sampled or driven on CLKIN edges when PCLKENDBG is asserted.

Table A.21. Debug interface signals

Signal	Direction	Description
PCLKENDBG	Input	Clock enable for APB buses.
PSELDBGm	Input	Selects the external debug interface.
PADDRDBGm[11:2]	Input	Programming address.
PADDRDBG31m	Input	Programming address.
PRDATADBGm[31:0]	Output	Read data bus.
PWDATADBGm[31:0]	Input	Write data bus.
PENABLEDBGm	Input	Indicates second, and subsequent, cycle of a transfer.
PREADYDBGm	Output	Extends a APB transfer by the inserting wait states.
PSLVERRDBGm	Output	Slave-generated error response.
PWRITEDBGm	Input	Indicates access is a write transfer. Distinguishes between a read, LOW, and a write, HIGH.
PRESETDBGmn	Input	Reset debug domain debug logic.^[a]
DBGRESETmn	Input	Reset core domain debug logic.^[a]
^[a]Can be asserted asynchronously.

Table A.22 shows the debug miscellaneous signals.

Table A.22. Debug miscellaneous signals

Signal	Direction	Description
DBGENm	Input	Debug enable^[a]
NIDENm	Input	Non-invasive debug enable^[a]
EDBGRQm	Input	External debug request^[a]
DBGACKm	Output	Debug acknowledge
DBGRSTREQm	Output	Request for reset from debug logic
DBGTRIGGERm	Output	External debug request taken
COMMRXm	Output	DTRRX full
COMMTXm	Output	DTRTX empty
DBGRESTARTm	Input	External restart request^[a]
DBGRESTARTEDm	Output	Handshake for DBGRESTARTm
DBGNOPWRDWN	Output	No power-down request
DBGROMADDR[31:12]	Input	Debug ROM physical address
DBGROMADDRV	Input	Debug ROM physical address valid
DBGSELFADDRm[31:12]	Input	Debug self-address offset
DBGSELFADDRVm	Input	Debug self-address offset valid
^[a]Can be asserted asynchronously.

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