1.1. About the processor

The Cortex-R5 processor is a mid-range CPU for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput. The pipeline has a single Arithmetic Logic Unit (ALU), but implements limited dual-issuing of instructions for efficient utilization of other resources such as the register file. A hardware Accelerator Coherency Port (ACP) is provided to reduce the requirement for slow software cache maintenance operations when sharing memory with other masters.

Interrupt latency is kept low by interrupting and restarting load-store multiple instructions, and by use of a dedicated peripheral port that enables low-latency access to an interrupt controller. The processor has Tightly-Coupled Memory (TCM) ports for low-latency and deterministic accesses to local RAM, in addition to caches for higher performance to general memory.

Error Checking and Correction (ECC) is used on the Cortex-R5 processor ports and in Level 1 (L1) memories to provide improved reliability and address safety-critical applications.

Many of the features, including the caches, TCM ports, and ECC are configurable so that a given processor implementation can be tailored to the application for efficient area usage.

Figure 1.1 shows the processor in a typical system.

Figure 1.1. Example Cortex-R5 system

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