A.2. Global signals

Table A.1 shows the processor global signals.

Table A.1. Global signals

SignalDirectionDescription
CLKINInputMaster processor clock.
ACPRESETnInputACP reset. Assert with nRESET0 and nRESET1 to reset the whole processor except the debug registers. This signal can be asserted asynchronously to CLKIN.
ACPIDLEOutputIndicate when uSCU is empty, for drain-and-power-down.
nRESETmInputCPU non-debug logic reset. These signals can be asserted asynchronously to CLKIN.
nSYSPORESETInputSystem power on reset.
nCPUHALTmInputProcessor halt after reset. These signals can be asserted asynchronously to CLKIN.
DBGNOCLKSTOPInputProcessor does not stop the clocks when entering standby mode.
nCLKSTOPPEDmOutput

When LOW, this indicates clock has been stopped because processor is in Standby Mode.

It is never asserted without one of WFIPIPESTOPPEDm or WFEPIPESTOPPEDm.

nWFEPIPESTOPPEDmOutputWhen LOW, this indicates that the CPU is in standby mode because of a WFE instruction. The CPU pipeline is inactive..
nWFIPIPESTOPPEDmOutputWhen LOW, this indicates the CPU is in standby mode because of a WFI instruction. The CPU pipeline is inactive.
EVENTImInputEvent input signal.
EVENTOmOutputEvent output signal.

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