11.1.1. FPU functionality

The FPU is an implementation of the ARM Vector Floating Point v3 architecture, with 16 double-precision registers (VFPv3-D16). It provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU supports all data-processing instructions and data types in the VFPv3 architecture as described in the ARM Architecture Reference Manual.

The FPU fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. The FPU does not support any data processing operations on vectors in hardware. Any data processing instruction that operates on a vector generates an Undefined Instruction exception. The operation can then be emulated in software if necessary.

Optionally, you can configure the FPU to support single-precision only.

Cortex-R5F does not implement either the half-precision conversion or fused-MAC extensions to the VFPv3 architecture.

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