3.8.1. Exception entry and exit summary

Table 3.4 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler.

Table 3.4. Exception entry and exit

Exception or entry

Recommended return instruction

Previous state

Notes

ARM R14_x

Thumb R14_x

SVC[a]

MOVS PC, R14_svc

IA + 4

IA + 2

Where the IA is the address of the SVC or Undefined Instruction.

UNDEF

Varies[b]

IA + 4

IA + 2

PABT

SUBS PC, R14_abt, #4

IA + 4

IA + 4

Where the IA is the address of instruction that had the Prefetch Abort.

FIQ

SUBS PC, R14_fiq, #4

IA + 4

IA + 4

Where the IA is the address of the instruction that was not executed because the FIQ or IRQ took priority.

IRQ

SUBS PC, R14_irq, #4

IA + 4

IA + 4

DABT

SUBS PC, R14_abt, #8

IA + 8

IA + 8

Where the IA is the address of the Load or Store instruction that generated the Data Abort.

RESET

NA

-

-

The value saved in R14_svc on reset is Unpredictable.

BKPT

SUBS PC, R14_abt, #4

IA + 4

IA + 4

Software breakpoint.

[a] Formerly SWI.

[b] The return instruction you must use after an Undefined Instruction exception has been handled depends on whether you want to retry the undefined instruction or not and, if not, on the size of the Undefined instruction.


Taking an exception

When taking an exception the processor:

  1. Preserves the address of the next instruction in the appropriate R14(LR). When the exception is taken from:

    ARM state

    The processor writes the address of the instruction into the LR, offset by a value (current IA + 4 or IA + 8 depending on the exception) that causes the program to resume from the correct place on return.

    Thumb state

    The processor writes the address of the instruction into the LR, offset by a value (current IA + 2, IA + 4 or IA + 8 depending on the exception) that causes the program to resume from the correct place on return.

  2. Copies the CPSR into the appropriate SPSR. Depending on the exception type, the processor might modify the IT execution state bits of the CPSR prior to this operation to facilitate a return from the exception.

  3. Forces the CPSR mode bits to a value that depends on the exception and clears the IT execution state bits in the CPSR.

  4. Sets the E bit based on the state of the EE bit in the SCTLR, see c1, System Control Register.

  5. The T bit is set based on the state of the TE bit in the SCTLR, see c1, System Control Register.

  6. Forces the PC to fetch the next instruction from the relevant exception vector.

The processor can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.

Leaving an exception

When an exception has completed, the exception handler must move the LR, minus an offset, to the PC. The offset varies according to the type of exception, as Table 3.4 shows.

Typically the return instruction is an arithmetic or logical operation with the S bit set and Rd = R15, so the processor copies the SPSR back to the CPSR. Alternatively, an LDM ..,{..pc}^ or RFE instruction can perform a similar operation if the return state has been pushed onto a stack.

Note

The action of restoring the CPSR from the SPSR:

  • Automatically restores the T, E, A, I, and F bits to the value they held immediately prior to the exception.

  • Normally resets the IT execution state bits to the values held immediately prior to the exception. If the exception handler wants to return to the following instruction, these bits might require to be manually advanced to avoid applying the incorrect condition codes to that instruction. For more information about the IT instruction elements and Undefined instructions, and an example of the exception handler code, see the ARM Architecture Reference Manual.

    Because SVC handlers are always expected to return after the SVC instruction, the IT execution state bits are automatically advanced when an exception is taken prior to copying the CPSR into the SPSR.

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