8.1. About the L1 memory system

The processor L1 memory system can be configured during implementation and integration. It can consist of:

The instruction-side and data-side can each optionally have their own L1 caches. The cache architecture is Harvard, that is, only instructions can be fetched from the I-Cache, and only data can be fetched from the D-Cache. In parallel with each of the caches are two areas of dedicated RAM accessible to both the instruction and data sides. These are regions of TCM. You can implement one TCM using the ATCM interface and up to two TCMs using the BTCM interface. Figure 8.1 shows this.

Memory accesses, required for fetching instructions and for data transfer instructions, are performed to the appropriate TCM if the address is in an enabled TCM region. Remaining instruction accesses and remaining data accesses that are not in a peripheral interface region are looked up in the appropriate L1 cache if they are cacheable. Accesses that are not serviced by the L1 memory system are passed to the L2 memory system through the AXI-master interface or one of the peripheral interfaces. See Chapter 9 Level Two Interface for more information about the L2 memory system.

Each TCM and cache can be configured at implementation time to have an error detection and correction scheme to protect the data stored in the memory from errors. Each TCM interface also has support for logic external to the processor to tell the processor that an error has occurred.

The MPU handles accesses to both the instruction and data sides. The MPU is responsible for protection checking, address access permissions, and memory attributes for all accesses. Some of these attributes can be passed to the L2 memory system through the AXI master or peripheral ports. See Chapter 7 Memory Protection Unit for more information about the MPU.

The L1 memory system includes a monitor for exclusive accesses. Exclusive load and store instructions, for example LDREX and STREX, can be used with the appropriate memory monitoring to provide inter-process or inter-processor synchronization and semaphores. See the ARM Architecture Reference Manual for more information. The internal monitor can handle some exclusive monitoring internally to the processor, see Internal exclusive monitor for more information.

Figure 8.1. Memory system block diagram

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511