A.5.6. ACP slave port error detection signals

Table A.10 shows the ACP slave port error detection signals. These signals are only generated if the processor is configured to include AXI bus parity. See Configurable options for more information.

Table A.10. ACP slave port error detection signals

SignalDirectionDescription
ACPSFATAL[1:0]OutputFatal error, per channel, {B,AW}
AWADDRPTYCS[3:0]InputParity bits for AWADDRCS[a]
AWCTLPTYCS[3:0]InputParity bits for the rest of the write address channel[a]
AWRPTYCSOutputParity bit for AWREADYCS
AWUSERPTYCSInputParity bit for sideband signals[a]
AWVPTYCSInputParity bit for AWVALIDCS
BCTLPTYCS[1:0]OutputParity for buffered response signal[a]
BRPTYCSOutputParity bit for BREADYCS
BVPTYCSOutputParity bit for BVALIDCS
BUSERPTYCSOutputParity bit for sideband signals[a]

[a] This is an AXI extension signal.


Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511