A.5.7. ACP master port

Table A.11 shows the ACP master port signals.

Table A.11. ACP master port signals

SignalDirectionDescription
Write Address Channel  
 AWIDCM[1:0]OutputThe identification tag for the write address group of signals.
 AWADDRCM[31:0]OutputTransfer start address
 AWLENCM[3:0]OutputWrite transfer burst length.
 AWSIZECM[2:0]OutputIndicates the size of the transfer.
 AWBURSTCM[1:0]OutputWrite burst type.
 AWLOCKCM[1:0]OutputLock signal.
 AWCACHECM[3:0]Output

Provides decode information for outer attributes:

b0000 = Strongly Ordered.

b0001 = Device.

b0011 = Normal, Non-cacheable.

b0110 = Normal, Cacheable. write-through.

b1111 = Normal, Cacheable. write-back, write allocation.

b0111 = Normal, Cacheable. write-back, no write allocation.

Note

The AXI specification describes these encodings using the pre-ARMv6 terms such as cacheable-bufferable. These terms are equivalent to the ARMv6 memory-type descriptions such as Normal, Non-cacheable used here.

 AWPROTCM[2:0]OutputProtection type.
 AWCOHERENTCMOutputRequire caches to be made coherent with this access.[a]
 AWUSERCM[3:0]OutputFor transmission of other sideband information.[a]
 AWVALIDCMOutputIndicates address and control are valid.
 AWREADYCMInputAddress ready. The slave uses this signal to indicate it is ready to accept the address.
Write Response Channel  
 BIDCM[1:0]InputThe identification tag for the write response signal.
 BRESPCM[1:0]InputWrite response
 BUSERCM[3:0]InputFor transmission of other sideband information.[a]
 BVALIDCMInputIndicates that a valid write response is available.
 BREADYCMOutputIndicates that the CPU is ready to accept write response.

[a] This is an AXI extension signal.


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