Cortex-R5 and Cortex-R5F Technical Reference ManualRevision: r1p1
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A.5.10. AXI peripheral port error detection signals

Table A.14 shows the AXI peripheral port error detection signals. These signals are only generated if the processor is configured to include AXI bus parity. See Configurable options for more information.

Table A.14. AXI peripheral port error detection signals

SignalDirectionDescription
ARADDRPTYPm[3:0]OutputParity bits for ARADDRPm[a]
ARCTLPTYPm[3:0]OutputParity bits for the rest of the read address channel[a]
ARRPTYPmInputParity bit for ARREADYPm
ARVPTYPmOutputParity bit for ARVALIDPm
AWADDRPTYPm[3:0]OutputParity bits for AWADDRPm[a]
AWCTLPTYPm[3:0]OutputParity bits for the rest of the write address channel[a]
AWRPTYPmInputParity bit for AWREADYPm
AWVPTYPmOutputParity bit for AWVALIDPm
PPXCORRmOutput

Correctable error on RRESPPm[b]

PPXFATALm[4:0]OutputFatal error, one bit for each channel {R,AR,B,W,AW}
RCTLPTYPm[1:0]InputParity bits for the rest of the read data channel[a]
RERRCODEPm[6:0]InputECC code for RDATAPm[a]
RRPTYPmOutputParity bit for RREADYPm
RVPTYPmInputParity bit for RVALIDPm
WCTLPTYPm[2:0]OutputParity bits for the rest of the write data channel[a]
WERRCODEPm[6:0]OutputECC code for WDATAPm[a]
WRPTYPmInputParity bit for WREADYPm
WVPTYPmOutputParity bit for WVALIDPm

[a] This is an AXI extension signal.

[b] Address is reported on MERRADDRm, listed in Table A.6.


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