B.6.1. Example interlocks

Table B.8 shows interlock examples using USAD8 and USADA8 instructions.

Table B.8. Example interlocks

Instruction sequence

USAD8 R1,R2,R3
ADD R5,R6,R1

Takes three cycles because USAD8 has a Result Latency of two, and the ADD requires the result of the USAD8 instruction.

USAD8 R1,R2,R3
ADD R5,R6,R1

Takes three cycles. The MOV instruction is scheduled during the Result Latency of the USAD8 instruction.

USAD8 R1,R2,R3
USADA8 R1,R4,R5,R1

Takes two cycles. The Result Latency is one less because the result is used as the accumulate for a subsequent USADA8 instruction.

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