Cortex-R5 and Cortex-R5F Technical Reference Manual: 3.6.1. The register set

3.6.1. The register set

In the processor the same register set is used in both the ARM and Thumb states. Sixteen general registers and one or two status registers are accessible at any time. In Privileged modes, alternative mode-specific banked registers become available. Figure 3.3 shows the registers that are available in each mode.

The register set contains 16 directly-accessible registers, R0-R15. Another register, the Current Program Status Register (CPSR), contains condition code flags, status bits, and current mode bits. Registers R0-R12 are general-purpose registers that hold either data or address values. Registers R13, R14, R15, and the CPSR have these special functions:

Stack pointer

Software normally uses register R13 as a Stack Pointer (SP). The SRS and RFE instructions use Register R13.

Link Register

You can use R14 as a general-purpose register at all other times. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt, and R14_und similarly hold the return values when interrupts and exceptions are taken, or when BL or BLX instructions are executed within interrupt or exception routines.

Program Counter

in ARM state this is word-aligned
in Thumb state this is halfword-aligned.

Note

There are special cases for reading R15:

reading the address of the current instruction plus, either:
- 4 in Thumb state
- 8 in ARM state.
reading 0x00000000 (zero).

There are special cases for writing R15:

causing a branch to the address that was written to R15
ignoring the value that was written to R15
writing bits [31:28] of the value that was written to R15 to the condition flags in the CPSR, and ignoring bits [27:0] (used for the MRC instruction only).

You must not assume any of these special cases unless it is explicitly stated in the instruction description. Instead, you must treat instructions with register fields equal to R15 as Unpredictable.

For more information, see the ARM Architecture Reference Manual.

In Privileged modes, another register, the Saved Program Status Register (SPSR), is accessible. This contains the condition code flags, status bits, and current mode bits saved as a result of the exception that caused entry to the current mode.

Banked registers have a mode identifier that indicates which mode they relate to. Table 3.1lists these identifiers.

Table 3.1. Register mode identifiers

Mode	Mode identifier
User	usr^[a]
Fast interrupt	fiq
Interrupt	irq
Supervisor	svc
Abort	abt
System	usr^a
Undefined	und
^[a]The `usr` identifier is usually omitted from register names. It is only used in descriptions where the User or System mode register is specifically accessed from another operating mode.

FIQ mode has seven banked registers mapped to R8-R14 (R8_fiq-R14_fiq). As a result, many FIQ handlers do not have to save any registers.

The Supervisor, Abort, IRQ, and Undefined modes each have alternative mode-specific registers mapped to R13 and R14, permitting a private stack pointer and link register for each mode.

Figure 3.3 shows the register set, and those registers that are banked.

Figure 3.3. Register organization

Note

For 16-bit Thumb instructions, the high registers, R8-R15, are not part of the standard register set. You can use special variants of the MOV instruction to transfer a value from a low register, in the range R0-R7, to a high register, and from a high register to a low register. The CMP instruction enables you to compare high register values with low register values. The ADD instruction enables you to add high register values to low register values. For more information, see the ARM Architecture Reference Manual.

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