9.4.2. TCM ECC support

The TCMs can support ECC, as described in TCM internal error detection and correction. If a write transaction is issued to the AXI slave, the slave interface calculates the required ECC bits to store to the TCM. If the write data width is smaller than the ECC chunk size then a read-modify-write sequence is automatically performed by the AXI slave.

Note

It is important to ensure that all writes to TCMs that do not contain the correct ECC bits for their data, such as uninitialized RAMs, are performed with a size of at least the ECC chunk size or with error checking disabled.

If a read transaction is issued to the AXI slave, the slave interface reads the ECC bits and, if error checking is enabled for the appropriate TCM, checks the data for errors. If the interface detects a correctable error, it corrects it inline and returns the correct data on the AXI bus. It does not update the data in the TCM to correct it. If the interface detects an uncorrectable error, it generates a SLVERR error response to the AXI transaction.

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