9.4.4. Cache parity and ECC support

When the caches support parity or ECC, the AXI slave interface permits direct read and write access to the parity or ECC code bits. No errors are detected automatically, and on writes the AXI slave does not automatically generate the correct parity or ECC code values.


The AXI slave interface provides read/write access to the cache RAMs for functional test. It is not suitable for preloading the caches.

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