Using this book

This book is organized into the following chapters:

Chapter 1 Introduction

Read this for an introduction to the processor and descriptions of the major functional blocks.

Chapter 2 Functional Description

Read this for a description of the functionality of the product.

Chapter 3 Programmers Model

Read this for a description of the processor registers and programming information.

Chapter 4 System Control

Read this for a description of the system control coprocessor registers and programming information.

Chapter 5 Prefetch Unit

Read this for a description of the functions of the Prefetch Unit (PFU), including dynamic branch prediction and the return stack.

Chapter 6 Events and Performance Monitor

Read this for a description of the Performance Monitoring Unit (PMU) and the event bus.

Chapter 7 Memory Protection Unit

Read this for a description of the Memory Protection Unit (MPU) and the access permissions process.

Chapter 8 Level One Memory System

Read this for a description of the Level One (L1) memory system.

Chapter 9 Level Two Interface

Read this for a description of the features of the Level Two (L2) interface not covered in the AMBA AXI Protocol Specification.

Chapter 10 Power Control

Read this for a description of the power control facilities.

Chapter 11 FPU Programmers Model

Read this for a description of the Floating Point Unit (FPU) support in the Cortex-R5F processor.

Chapter 12 Debug

Read this for a description of the debug support.

Chapter 13 Integration Test Registers

Read this for a description of the Integration Test Registers, and of integration testing of the processor with an ETM-R5 trace macrocell.

Appendix A Signal Descriptions

Read this for a description of the inputs and outputs of the processor.

Appendix B Cycle Timings and Interlock Behavior

Read this for a description of the instruction cycle timing and instruction interlocks.

Appendix C ECC Schemes

Read this for a description of how to select the Error Checking and Correction (ECC) scheme depending on the Tightly-Coupled Memory (TCM) configuration.

Appendix D Memory Ordering

Read this for a description of the processor memory ordering and the virtual AXI peripheral interface.

Appendix E Revisions

Read this for a description of the technical changes between released issues of this book.

Glossary

Read this for definitions of terms used in this book.

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