Cortex-R5 Technical Reference Manual: 9.7.7. AXI peripheral port transfers

9.7.7. AXI peripheral port transfers

The processor conforms to the AXI3 specification, but it does not generate all the AXI transaction types that the specification permits. This section describes the types of AXI transactions that the Cortex-R5 AXI peripheral port does not generate. If you are designing an AXI slave to work only with the Cortex-R5 processor AXI peripheral port, you can take advantage of these restrictions and the interface attributes to simplify the slave.

This section also contains tables that show some examples of the types of AXI burst that the processor generates. However, because a particular type of transaction is not shown here does not mean that the processor does not generate such a transaction.

Note

An AXI slave device connected to the Cortex-R5 AXI master port must be capable of handling every kind of transaction permitted by the AXI specification, except where there is an explicit statement in this chapter that such a transaction is not generated. You must not infer any additional restrictions from the example tables given.

Restrictions on AXI peripheral transfers describes restrictions on the type of transfers that the Cortex-R5 AXI peripheral port generates. If a CPUm exists and is powered up, BREADYPm and RREADYPm are always asserted. They are, however, deasserted when the CPU enters Dormant or Shutdown mode. You must not make any assumptions about the AXI handshaking signals, except that they conform to the AMBA AXI3 Protocol Specification.

The following sections give examples of transfers generated by the LLPP AXI interface:

Restrictions on AXI peripheral transfers

The Cortex-R5 AXI peripheral port applies the following restrictions to the AXI transactions it generates:

A burst never transfers more than eight bytes
The burst length is never more than two transfers
No transaction ever crosses a 8-byte boundary in memory
All bursts are incrementing (INCR) bursts
If the transfer size is 8-bits or 16-bits then the burst length is always one transfer
The transfer size is never greater than 32 bits
All transactions are non-secure data accesses
Transactions to Device and Strongly Ordered memory are always to addresses that are aligned for the transfer size
Exclusive and Locked accesses are always to addresses that are aligned for the transfer size
Write data is never interleaved
ID values can only be 0 or 1 indicating normal AXI or virtual AXI respectively.

Strongly Ordered and Device transactions

A load or store instruction to or from Strongly Ordered or Device memory always generates AXI transactions of the same size as the instruction implies. All accesses using LDM, STM, LDRD, or STRD instructions to Strongly Ordered or Device memory occur as 32-bit transfers.

LDRB

Table 9.46 shows the values of ARADDRPm, ARBURSTPm, ARSIZEPm, and ARLENPm for LDRB from bytes 0-3 in Strongly Ordered or Device memory.

Table 9.46. LDRB transfers

Address[1:0]	ARADDRPm	ARBURSTPm	ARSIZEPm	ARLENPm
`0x0` (byte 0)	`0x00`	Incr	8-bit	1 data transfer
`0x1` (byte 1)	`0x01`	Incr	8-bit	1 data transfer
`0x2` (byte 2)	`0x02`	Incr	8-bit	1 data transfer
`0x3` (byte 3)	`0x03`	Incr	8-bit	1 data transfer

LDRH

Table 9.47 shows the values of ARADDRPm, ARBURSTPm, ARSIZEPm, and ARLENPm for LDRH from halfwords 0-1 in Strongly Ordered or Device memory.

Table 9.47. LDRH transfers

Address[1:0]	ARADDRPm	ARBURSTPm	ARSIZEPm	ARLENPm
`0x0` (halfword 0)	`0x00`	Incr	16-bit	1 data transfer
`0x2` (halfword 1)	`0x02`	Incr	16-bit	1 data transfer

Note

A load of a halfword from Strongly Ordered or Device memory addresses 0x1 or 0x3 generates an alignment fault.

LDR or LDM that transfer one register

Table 9.48 shows the values of ARADDRPm, ARBURSTPm, ARSIZEPm, and ARLENPm for an LDR or an LDM that transfers one register, an LDM1, in Strongly Ordered or Device memory.

Table 9.48. LDR or LDM transfers

Address[1:0]	ARADDRPm	ARBURSTPm	ARSIZEPm	ARLENPm
`0x0` (word 0)	`0x00`	Incr	32-bit	1 data transfer

Note

A load of a word from Strongly Ordered or Device memory addresses 0x1, 0x2, or 0x3 generates an alignment fault.

LDM that transfers five registers

Table 9.49 shows the values of ARADDRPm, ARBURSTPm, ARSIZEPm, and ARLENPm for an LDM that transfers five registers, an LDM5, in Strongly Ordered or Device memory.LDM transfers

Table 9.49. LDM transfers

Address[2:0]	ARADDRPm	ARBURSTPm	ARSIZEPm	ARLENPm
`0x0` (word 0)	`0x00`	Incr	32-bit	2 data transfers
	`0x08`	Incr	32-bit	2 data transfers
	`0x10`	Incr	32-bit	1 data transfer
`0x4` (word 1)	`0x04`	Incr	32-bit	1 data transfer
	`0x08`	Incr	32-bit	2 data transfers
	`0x10`	Incr	32-bit	2 data transfers

Note

A load-multiple from memory addresses 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment fault.

STRB

Table 9.50 shows the values of AWADDRPm, AWBURSTPm, AWSIZEPm, and AWLENPm for an STRB from bytes 0-3 in Strongly Ordered or Device memory.

Table 9.50. STRB transfers

Address[1:0]	AWADDRPm	AWBURSTPm	AWSIZEPm	AWLENPm	WSTRBPm
`0x0` (byte 0)	`0x00`	Incr	8-bit	1 data transfer	b0001
`0x1` (byte 1)	`0x01`	Incr	8-bit	1 data transfer	b0010
`0x2` (byte 2)	`0x02`	Incr	8-bit	1 data transfer	b0100
`0x3` (byte 3)	`0x03`	Incr	8-bit	1 data transfer	b1000

STRH

Table 9.51 shows the values of AWADDRPm, AWBURSTPm, AWSIZEPm, and AWLENPm for an STRB from halfwords 0-1 in Strongly Ordered or Device memory.

Table 9.51. STRH transfers

Address[1:0]	AWADDRPm	AWBURSTPm	AWSIZEPm	AWLENPm	WSTRBPm
`0x0` (halfword 0)	`0x00`	Incr	16-bit	1 data transfer	b0011
`0x2` (halfword 1)	`0x02`	Incr	16-bit	1 data transfer	b1100

Note

A store of a halfword from Strongly Ordered or Device memory addresses 0x1, 0x3, 0x5, or 0x7 generates an alignment fault.

STR or STM of one register

Table 9.52 shows the values of AWADDRm, AWBURSTPm, AWSIZEPm, and AWLENPm for an STR or an STM that transfers one register, an STM1, to Strongly Ordered or Device memory.

Table 9.52. STR or STM transfers

Address[1:0]	AWADDRPm	AWBURSTPm	AWSIZEPm	AWLENPm	WSTRBPm
`0x0` (word 0)	`0x00`	Incr	32-bit	1 data transfer	b1111

Note

A store of a word to Strongly Ordered or Device memory addresses 0x1, 0x2, or 0x3 generates an alignment fault.

STM of five registers

Table 9.53 shows the values of AWADDRm, AWBURSTPm, AWSIZEPm, and AWLENPm for an STM that writes five registers, an STM5, over the AXI peripheral port to Strongly Ordered or Device memory.

Table 9.53. STM transfers

Address[2:0]	AWADDRPm	AWBURSTPm	AWSIZEPm	AWLENPm	WSTRBPm
`0x00` (word 0)	`0x00`	Incr	32-bit	2 data transfers	b1111 b1111
	`0x08`	Incr	32-bit	2 data transfers	b1111 b1111
	`0x10`	Incr	32-bit	1 data transfer	b1111
`0x04` (word 1)	`0x04`	Incr	32-bit	1 data transfer	b1111
	`0x08`	Incr	32-bit	2 data transfers	b1111 b1111
	`0x10`	Incr	32-bit	2 data transfers	b1111 b1111

Note

A store-multiple to address 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment fault.

Normal reads

Load instructions accessing Normal memory generate AXI peripheral port bursts that are always of 32-bit size and not necessarily the same size or length as the instruction implies. The tables in this section give examples of the types of AXI transaction that might result from various load instructions, accessing various addresses in Normal memory. They are provided as examples only, and are not an exhaustive description of the AXI transactions.

Table 9.54 shows possible values of ARADDRm, ARBURSTPm, ARSIZEPm, and ARLENPm for an LDRH from bytes 0-7 in Normal memory.

Table 9.54. LDRH transfers

Address[1:0]	ARADDRPm	ARBURSTPm	ARSIZEPm	ARLENPm
`0x0` (byte 0)	`0x00`	Incr	32-bit	1 data transfer
`0x1` (byte 1)	`0x00`	Incr	32-bit	1 data transfer
`0x2` (byte 2)	`0x00`	Incr	32-bit	1 data transfer
`0x3` (byte 3)	`0x00`	Incr	32-bit	2 data transfers
`0x4` (byte 4)	`0x04`	Incr	32-bit	1 data transfer
`0x5` (byte 5)	`0x04`	Incr	32-bit	1 data transfer
`0x6` (byte 6)	`0x04`	Incr	32-bit	1 data transfer
`0x7` (byte 7)^[a]	`0x04`	Incr	32-bit	1 data transfer
`0x7` (byte 7)^[a]	`0x08`	Incr	32-bit	1 data transfer
^[a]AXI peripheral port transactions do not cross a double word boundary.

Table 9.55 shows possible values of ARADDRm, ARBURSTPm, ARSIZEPm, and ARLENPm for an LDR or an LDM that transfers one register, an LDM1, to Normal memory.

Table 9.55. LDR or LDM transfers

Address[1:0]	ARADDRPm	ARBURSTPm	ARSIZEPm	ARLENPm
`0x0` (byte 0) (word 0)	`0x00`	Incr	32-bit	1 data transfer
`0x1` (byte 1)	`0x00`	Incr	32-bit	2 data transfers
`0x2` (byte 2)	`0x00`	Incr	32-bit	2 data transfers
`0x3` (byte 3)	`0x00`	Incr	32-bit	2 data transfers
`0x4` (byte 4) (word 1)	`0x04`	Incr	32-bit	1 data transfer
`0x5` (byte 5)	`0x04`	Incr	32-bit	1 data transfer
`0x5` (byte 5)	`0x08`	Incr	32-bit	1 data transfer
`0x6` (byte 6)	`0x04`	Incr	32-bit	1 data transfer
`0x6` (byte 6)	`0x08`	Incr	32-bit	1 data transfer
`0x7` (byte 7)	`0x04`	Incr	32-bit	1 data transfer
`0x7` (byte 7)	`0x08`	Incr	32-bit	1 data transfer

Table 9.56 shows possible values of ARADDRm, ARBURSTPm, ARSIZEPm, and ARLENPm for an LDM that transfers five registers, an LDM5, to Normal memory.

Table 9.56. LDM transfers

Address[1:0]	ARADDRPm	ARBURSTPm	ARSIZEPm	ARLENPm
`0x0` (word 0)	`0x00`	Incr	32-bit	2 data transfers
	`0x08`	Incr	32-bit	2 data transfers
	`0x10`	Incr	32-bit	1 data transfer
`0x4` (word 1)	`0x04`	Incr	32-bit	1 data transfer
	`0x08`	Incr	32-bit	2 data transfers
	`0x10`	Incr	32-bit	2 data transfers

Normal Writes

Store instructions accessing Normal memory generate AXI peripheral port bursts that are always of 32-bit size and not necessarily the same size or length as the instruction implies. The AXI peripheral port asserts byte-lane strobes, WSTRBPm[3:0], to ensure that only the bytes that were written by the instruction are updated.

The tables in this section give examples of the types of AXI transaction that might result from various store instructions, accessing various addresses in Normal memory. They are provided as examples only, and are not an exhaustive description of the AXI transactions.

Table 9.57 shows the values of AWADDRPm, AWBURSTPm, AWSIZEPm, and AWLENPm for an STRH to Normal memory.

Table 9.57. STRH transfers

Address[1:0]	AWADDRPm	AWBURSTPm	AWSIZEPm	AWLENPm	WSTRBPm
`0x0` (byte 0)	`0x00`	Incr	32-bit	1 data transfer	b0011
`0x1` (byte 1)	`0x00`	Incr	32-bit	1 data transfer	b0110
`0x2` (byte 2)	`0x00`	Incr	32-bit	1 data transfer	b1100
`0x3` (byte 3)	`0x00`	Incr	32-bit	2 data transfers	b1000 b0001
`0x4` (byte 4)	`0x04`	Incr	32-bit	1 data transfer	b0011
`0x5` (byte 5)	`0x04`	Incr	32-bit	1 data transfer	b0110
`0x6` (byte 6)	`0x04`	Incr	32-bit	1 data transfer	b1100
`0x7` (byte 7)	`0x04`	Incr	32-bit	1 data transfer	b1000
`0x7` (byte 7)	`0x08`	Incr	32-bit	1 data transfer	b0001

Table 9.58 shows the values of AWADDRPm, AWBURSTPm, AWSIZEPm, and AWLENPm for an STR or an STM that transfers one register, an STM1, to Normal memory.

Table 9.58. STR or STM transfers

Address[1:0]	AWADDRPm	AWBURSTPm	AWSIZEPm	AWLENPm	WSTRBPm
`0x0` (byte 0) (word 0)	`0x00`	Incr	32-bit	1 data transfer	b1111
`0x1` (byte 1)	`0x00`	Incr	32-bit	2 data transfers	b1110 b0001
`0x2` (byte 2)	`0x00`	Incr	32-bit	2 data transfers	b1100 b0011
`0x3` (byte 3)	`0x00`	Incr	32-bit	2 data transfers	b1000 b0111
`0x4` (byte 4) (word 1)	`0x04`	Incr	32-bit	1 data transfer	b1111
`0x5` (byte 5)	`0x04`	Incr	32-bit	1 data transfer	b1110
`0x5` (byte 5)	`0x08`	Incr	32-bit	1 data transfer	b0001
`0x6` (byte 6)	`0x04`	Incr	32-bit	1 data transfer	b1100
`0x6` (byte 6)	`0x08`	Incr	32-bit	1 data transfer	b0011
`0x7` (byte 7)	`0x04`	Incr	32-bit	1 data transfer	b1000
`0x7` (byte 7)	`0x08`	Incr	32-bit	1 data transfer	b0111

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