Cortex-R5 Technical Reference ManualRevision: r1p2
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4.3.2. c0, Main ID Register

The MIDR characteristics are:

Purpose

Returns the device ID code that contains information about the processor

Usage constraints

The MIDR is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.3.

Figure 4.7 shows the shows the MIDR bit assignments.

Figure 4.7. MIDR bit assignments

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Table 4.3 shows the MIDR bit assignments.

Table 4.3. MIDR bit assignments

Bits

NameFunction
[31:24]Implementer

Indicates implementer.

0x41 = ARM Limited.

[23:20]Variant

Identifies the major revision of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status.

[19:16]Architecture

Indicates the architecture version.

0xF = see feature registers.

[15:4]Primary part number

Indicates processor part number.

0xC15 = Cortex-R5.

[3:0]Revision

Identifies the minor revision of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status.


Note

If an MRC instruction is executed with CRn = c0, Opcode_1 = 0, CRm = c0, and an Opcode_2 value corresponding to an unimplemented or reserved ID register, the system control coprocessor returns the value of the MIDR.

To access the MIDR, read CP15 with:

MRC p15, 0, <Rd>, c0, c0, 0 ; Read MIDR

For more information on the processor features, see The Processor Feature Registers.

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