Cortex-R5 Technical Reference Manual: 4.3.4. c0, TCM Type Register

The TCMTR characteristics are:

Purpose

Informs the processor of the number of ATCMs and BTCMs in the system

Usage constraints

The TCMTR is:

Configurations

Available in all processor configurations.

Attributes

See Table 4.5.

Figure 4.9 shows the TCMTR bit assignments.

Figure 4.9. TCMTR bit assignments

Table 4.5 shows the TCMTR bit assignments.

Table 4.5. TCMTR bit assignments

Bits	Name	Function
[31:29]	-	Always 0, indicating v6 format TCMTR.
[28:19]	-	SBZ.
[18:16]	BTCM	Specifies the number of BTCMs implemented. This is always set to `b001` because the processor has one BTCM.
[15:3]	-	SBZ.
[2:0]	ATCM	Specifies the number of ATCMs implemented. Always set to b001. The processor has one ATCM.

To access the TCMTR, read CP15 with:

MRC p15, 0, <Rd>, c0, c0, 2 ; Returns TCMTR

The ATCM and BTCM fields in the TCMTR occupy the same space respectively as the ITCM and DTCM fields as defined by the ARM architecture. These fields, and the corresponding TCM interfaces, can be considered equivalent to those defined in the architecture.
The ARM architecture requires only the ITCM to be accessible from both instruction and data sides. In the Cortex-R5 processor, both ATCM and BTCM are accessible from both instruction and data sides.

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