| Copyright © 2010-2011 ARM. All rights reserved. | ARM DDI 0460D |
| Non-Confidential | ID092411 |
 PDF version | |
| Home > Level One Memory System > Error detection events |
| |||
| Home > Level One Memory System > Error detection events | |||
The processor generates a number of events related to the internal error detection and correction schemes in the TCMs and caches. For more information, see Table 6.1. This section describes:
| Copyright © 2010-2011 ARM. All rights reserved. | ARM DDI 0460D |
| Non-Confidential | ID092411 |
| PDF version | |
| Home > Level One Memory System > Error detection events |