12.8.1. Entering debug state
When a debug event occurs while the processor is in Halting
debug-mode, it switches to a special state called debug
state so the debugger can take control. You can configure
Halting debug-mode by setting DBGDSCR[14].
If a halting debug event occurs, the processor enters debug
state even when Halting debug-mode is not configured. While the
processor is in debug state, the PC does not increment on instruction execution.
If the PC is read at any point after the processor has entered debug
state, but before an explicit PC write, it returns a value as described
in Table 12.40, depending
on the previous state and the type of debug event.
Table 12.40 shows
the read PC value after debug state entry for different debug events.
Table 12.40. Read PC value after debug state entry
| Debug event | ARM | Thumb | Return address (RA) meaning |
|---|
| Breakpoint | RA+8 | RA+4 | Breakpointed instruction address. |
| Watchpoint | RA+8 | RA+4 | Watchpointed instruction address. |
BKPT instruction | RA+8 | RA+4 | BKPT instruction address. |
| Vector catch | RA+8 | RA+4 | Vector address. |
| External debug request signal activation | RA+8 | RA+4 | Address of the instruction where the execution
resumes. |
| Debug state entry request command | RA+8 | RA+4 | Address of the instruction where the execution
resumes. |
| OS unlock event | RA+8 | RA+4 | Address of the instruction where the execution
resumes. |
| CTI debug request signal | RA+8 | RA+4 | Address of the instruction where the execution
resumes. |
PDF version